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Schematic Diagrams
Processor 2/7- CLK, MISC
Processor Pullups/Pull downs
VCCIO_OUT
D
Sheet 3 of 46
Processor 2/7-CLK,
C
MISC
B
SSC CLOCK TERMINATION
STUFF R4R15 & R4R12
ONLY WHEN SSC CLOCK
NOT USED
A
B - 4 Processor 2/7- CLK, MISC
5
4
Haswell Processor 2/7 ( CLK,MISC,JTAG )
R383
R383
62_04
62_04
H_PROCHOT#
R363
R363
10K_04
10K_04
H_CPUPW RGD_R
TRACE WIDTH 10MIL, LENGTH <500MILS
SKTOCC#
H_CATERR#
R379
R379
*10mil_short
*10mil_short
H_PECI_ISO
24,36
H_PECI
VCCST
R382
R382
56_1%_04
56_1%_04
H_PROCHOT#_D
41
H_PROCHOT#
H_THRMTRIP_R_N
24
H_THRMTRIP_R_N
22
H_PM_SYNC
H_CPUPW RGD
R364
R364
*10mil_short
*10mil_short
H_CPUPW RGD_R
24
H_CPUPW RGD
PMSYS_PW RGD_BUF
R49
R49
130_1%_04
130_1%_04
VDDPW RGOOD_R
BUF_CPU_RST#
R380
R380
*0_04
*0_04
CPU_RST_N_R
R381
R381
*10mil_short
*10mil_short
24
CPU_RST_N
28
PCH_CK_DP_N
28
PCH_CK_DP_P
28
PCH_SSC_N
28
PCH_SSC_P
28
CLK_EXP_N
28
CLK_EXP_P
VCCIO_OUT
R24
R24
*10K_04
*10K_04
1.05V_LAN_M
VCCST
PCH_SSC_P
PCH_SSC_N
R65
R65
*0_04
*0_04
R25
R25
*10K_04
*10K_04
C104
C104
C103
C103
*22u_6.3V_X5R_08
*22u_6.3V_X5R_08
*22u_6.3V_X5R_08
*22u_6.3V_X5R_08
Buffered reset to CPU
R376
R376
*2K_1%_04
*2K_1%_04
BUF_CPU_RST#
23,30
PLT_RST#
R391
R391
*1K_1%_04
*1K_1%_04
5
4
3
U26B
U26B
Haswell rPGA EDS
Haswell rPGA EDS
AP32
MISC
MISC
AP3
SM_RCOMP_0
SKTOCC
SM_RCOMP_0
AR3
SM_RCOMP_1
SM_RCOMP_1
AN32
AP2
SM_RCOMP_2
CATERR
SM_RCOMP_2
AR27
AN3
CPUDRAMRST#
PECI
SM_DRAMRST
AK31
FC
AM30
AR29
XDP_PRDY#
PROCHOT
PRDY
AM35
AT29
XDP_PREQ#
THERMTRIP
PREQ
AM34
XDP_TCLK
TCK
AN33
XDP_TMS
TMS
AM33
XDP_TRST#
TRST
AT28
AM31
XDP_TDI_R
PM_SYNC
TDI
AL34
AL33
XDP_TDO_R
PWRGOOD
TDO
AC10
AP33
XDP_DBR_R
SM_DRAMPWROK
DBR
AT26
PLTRSTIN
AR30
XDP_BPM0
BPM_N_0
AN31
XDP_BPM1
BPM_N_1
G28
AN29
XDP_BPM2
DPLL_REF_CLKN
BPM_N_2
H28
AP31
XDP_BPM3
DPLL_REF_CLKP
BPM_N_3
PCH_SSC_N
F27
AP30
XDP_BPM4
SSC_DPLL_REF_CLKN
BPM_N_4
PCH_SSC_P
E27
AN28
XDP_BPM5
SSC_DPLL_REF_CLKP
BPM_N_5
D26
AP29
XDP_BPM6
BCLKN
BPM_N_6
E26
AP28
XDP_BPM7
BCLKP
BPM_N_7
2 OF 9
2 OF 9
H_PROCHOT#
Q15
Q15
G
C107
C107
36
H_PROCHOT_EC
MTN7002ZHS3
MTN7002ZHS3
R377
R377
47p_50V_NPO_04
47p_50V_NPO_04
100K_04
100K_04
CAD Note: Capacitor need to be placed
close to buffer output pin
S3 circuit:- DRAM_RST# to memory
should be high during S3
V_VDDQ_DIMM
R399
R399
1K_04
1K_04
R392
R392
*0_04
*0_04
Q18
Q18
MTN7002ZHS3
MTN7002ZHS3
CPUDRAMRST#
S
D
R397
R397
1K_04
1K_04
DDR3_DRAMRST#
DRAMRST_CNTRL
4,21
R373
R373
C565
C565
4.99K_1%_04
4.99K_1%_04
0.047u_10V_X7R_04
0.047u_10V_X7R_04
4,5,9,10,40
V_VDDQ_DIMM
5,6
VCCIO_OUT
5,26,27,38,41,42
1.05V_LAN_M
2,12,17,20,24,25,28,29,31,33,35,37,38,40,42
6,9,10,11,12,19,20,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,41
3.3VS
3
2
1
H_THRMTRIP_R_N
R368
R368
CPU_RST_N
R374
R374
DDR3 Compensation Signals
SM_RCOMP_0
R387
R387
SM_RCOMP_1
R388
R388
SM_RCOMP_2
R386
R386
XDP_TCLK
R369
R369
XDP_TRST#
R370
R370
1.05V_LAN_M
PU/PD for JTAG signals
R365
R365
XDP_PREQ#
R442
R442
XDP_TMS
R448
R448
51_04
51_04
XDP_TDI_R
R454
R454
XDP_TDO_R
XDP_DBR_R
R385
R385
R366
R366
*100_04
*100_04
If PROCHOT# is not used,
then it must be terminated
with a 56-
+-5% pull-up
resistor to 1.05VS_VTT .
S3 circuit:- DRAM PWR GOOD lCIRCUIT
3.3V
3.3V
C102
C102
V_VDDQ_DIMM
R58
R58
R55
R55
R50
R50
1.82K_1%_04
1.82K_1%_04
1
22
PM_DRAM_PW RGD
4
2
U3
U3
R52
R52
3.32K_1%_04
3.32K_1%_04
*MC74VHC1G08DFT1G
*MC74VHC1G08DFT1G
R53
R53
*10mil_short
*10mil_short
9,10
Q2
Q2
G
34,37,40
SUSB
*MTN7002ZHS3
*MTN7002ZHS3
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
Title
Title
Title
[03] Haswell 2/7-CLK/MISC
[03] Haswell 2/7-CLK/MISC
[03] Haswell 2/7-CLK/MISC
3.3V
Size
Size
Size
Document Number
Document Number
Document Number
6-71-W65J0-D01
6-71-W65J0-D01
6-71-W65J0-D01
A3
A3
A3
6-7P-W 65J4-001
6-7P-W 65J4-001
6-7P-W 65J4-001
Date:
Date:
Date:
W ednesday, October 16, 2013
W ednesday, October 16, 2013
W ednesday, October 16, 2013
Sheet
Sheet
Sheet
2
1
1.05V_LAN_M
*100_04
*100_04
*75_04
*75_04
D
100_1%_04
100_1%_04
75_1%_04
75_1%_04
100_1%_04
100_1%_04
51_04
51_04
51_04
51_04
1.05V_LAN_M
*51_04
*51_04
*51_04
*51_04
*51_04
*51_04
3.3VS
1K_04
1K_04
C
B
PMSYS_PW RGD_BUF
R51
R51
R54
R54
*39_04
*39_04
*100K_04
*100K_04
A
Rev
Rev
Rev
1.0
1.0
1.0
3
3
3
of
of
of
46
46
46
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