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HDMI, CRT
HDMI PORT
FOR INTEL GRAPHIC OPTION
D04 W/O HDMI SHIFT
U5
C37
0.1u_10V_X7R_04
HDMI B_D2BP
39
[16]
HDMIB_D2BP_C
IN_D1+
HDMI B_D2BN
38
C38
0.1u_10V_X7R_04
[16]
HDMIB_D2BN_C
IN_D1-
42
C35
0.1u_10V_X7R_04
HDMI B_D1BP
[16]
HDMIB_D1BP_C
41
IN_D2+
C36
0.1u_10V_X7R_04
HDMI B_D1BN
[16]
HDMIB_D1BN_C
IN_D2-
C362
0.1u_10V_X7R_04
HDMI B_D0BP
45
[16]
HDMIB_D0BP_C
IN_D3+
HDMI B_D0BN
44
C361
0.1u_10V_X7R_04
[16]
HDMIB_D0BN_C
IN_D3-
48
C33
0.1u_10V_X7R_04
HDMI B_CLKBP
[16]
HDMIB_CLKBP_C
47
IN_D4+
C34
0.1u_10V_X7R_04
HDMI B_CLKBN
[16]
HDMIB_CLKBN_C
IN_D4-
HDMI _CTRLCLK
9
[16]
HDMI_CTRLCLK
SCL
HDMI _CTRLDATA
8
[16]
HDMI_CTRLDATA
SDA
PORTC_HPD
7
[16]
PORTC_HPD
HPD/HPDX
25
R37
* 4.7K_04
OE#
3.3VS
OE#
R38
* 0_04
DCC_EN#
32
R34
* 4.7K_04
3.3VS
DCC_EN
6
For PS8171- 499_1%_04
R344
* 3.4K_1%_04
REXT
REXT
R33
* 4.7K_04
PC0/PEQ
3
3.3VS
PC0/PEQ
R518
* 4.7K_04
4
R35
* 4.7K_04
PC1/PIO
3.3VS
PC1/PIO
R521
* 4.7K_04
R32
* 4.7K_04
DDCBUF_EN
34
3.3VS
DDCBUF_EN/DDCBUF
R524
* 4.7K_04
35
R26
* 4.7K_04
PRE/CFG
3.3VS
CFG/PRE
R527
* 4.7K_04
CEXT/RT_EN#
10
R555
* 4.7K_04
3.3VS
RT_EN#/CEXT
R556
* 4.7K_04
D 04
C549
*2. 2u_6.3V_X5R_04
PS8101»PPS8171®t²§
PS8171 2.2u_6.3V_X5R_04
* ASM1442
HPDX: Output level and polarity of HPD is defined by PIO
PIO=LOW:
HPD=HPD_SINK@3.3V CMOS output
PIO=High:
HPD=HPD_SINK#(inverted HPD)@0.9V
ASM1442(6-03-01442-030)
PIO: Internal pull down ~ 500k ohm
PS8171 (6-03-08171-030)
PEQ: TMDS iutput equalization control, 3 level CMOS input,
internal pull-down at ~ 500k ohm
DDCBUF: DDC Active Buffer enable and setting, 3 level CMOS input,
internal pull-down at ~ 500k ohm
PEQ=LOW:
Mid level EQ(Default)
DDCBUF=LOW:
No DDC active buffer, passive DDC level shifting
PEQ=High: High level EQ
DDCBUF=High:
Active DDC bufer enable, setting 1
PEQ=MID:
Low level EQ
DDCBUF=MID:
Active DDC bufer enable, setting 2
PRE: TMDS output driver pre-emphasis level setting,
3 level CMOS input, internal pull-down at ~ 500k ohm
PRE=LOW: No pre-emphasis
APD: Automatic power down managementl, 3 level CMOS input,
internal pull-up at ~ 500k ohm
APD=LOW:
Automatic power down disable
APD=High: Automatic power down enable
APD=MID:
Reserved
EMI0,EMI1: EMI reduction and filter setting, 3 level CMOS input,
EMI1 internal pull-up at ~ 500k ohm
EMI0 internal pull-down at ~ 500k ohm
[EMI1,EMI0]=HL: No EMI reduction
EMI0=High: Increased rise/fall time
MID, Increased rise/fall time,2nd
EMI1=LOW: EMI filter setting 1
MID: Reserved
CRT PORT
3.3VS
R479
R480
2.2K_04
2.2K_04
U13
10
[16]
DAC_DDCADATA
DDC_IN1
DDC_OUT1
11
[16]
DAC_DDCACLK
DDC_IN2
DDC_OUT2
13
[16]
DAC_HSY NC
SY NC_IN1
SY NC_OUT1
15
[16]
DAC_VSY NC
SY NC_IN2
SY NC_OUT2
1
5VS_CRT
VCC_SY NC
VI DEO_1
2
3.3VS
VCC_VIDEO
VI DEO_2
7
3.3VS
VCC_DDC
VI DEO_3
8
BY P
TPD7S019
12/14
D 04
22
HDMIB_DATA2P
OUT_D1+
23
HDMIB_DATA2N
OUT_D1-
19
HDMIB_DATA1P
OUT_D2+
20
HDMIB_DATA1N
OUT_D2-
16
HDMIB_DATA0P
OUT_D3+
17
HDMIB_DATA0N
OUT_D3-
13
HDMIB_CLOCKP
OUT_D4+
14
HDMIB_CLOCKN
OUT_D4-
PS8171 Internal pull up 100K
28
HDMIB_EXT1_SCL
SCL_SINK
29
HDMIB_EXT1_SDA
W/O level shift: 20K_1%_04
SDA_SINK
30
HDMI_HPD-C
R36
20K_1%_04
HPD_SINK
2
VCC[1]
15
VCC[3]
21
C42
C363
C43
C360
C365
VCC[4]
26
VCC[5]
40
* 0.1u_16V_Y 5V_04
*0.1u_16V_Y5V_04
* 0.1u_16V_Y 5V_04
* 0.1u_16V_Y 5V_04
* 0.1u_16V_Y 5V_04
VCC[7]
46
VCC[8]
11
APD/VCC
R516
* 0_04
PS8171 4.7K_04
3. 3VS
VCC[ 2]/APD
R517
* 4. 7K_04
33
EMI 1/VCC
R519
* 0_04
PS8171 *4. 7K_04
3. 3VS
VCC[6]/EMI1
R520
* 4. 7K_04
27
EMI 0/GND
R522
* 4. 7K_04
GND[6] /EMI0
3. 3VS
R523
* 0_04
PS8171 *4. 7K_04
12
RS/ GND
R525
* 4. 7K_04
PS8171 4.7K_04
3. 3VS
GND[3]/Res erv ed1
1
R526
* 0_04
GND[1]/Res erv ed0
5
PS8101»PPS8171®t²§
GND[2]
18
GND[4]
24
GND[5]
31
GND[7]
36
GND[8]
37
GND[9]
43
GND[10]
For ASM1442(¥i½ÕÀW¼e)
HDMIB_CLKBN
P IN 4 9 =G ND
R554
*2.2K_04
D 0 4
HDMIB_CLOCKN
HDMIB_CLOCKP
HDMIB_DATA1N
HDMIB_DATA1P
¹qªý»Ý¾aªñ¥æ¤e³B
RN17
RN19
* 0_8P4R_04_SHORT
* 0_8P4R_04_SHORT
HDMIB_D1BP
5
4
HDMIB_D1BP_M
5
4
HDMIB_DATA1P
6
3
6
3
HDMIB_D1BN
HDMIB_D1BN_M
HDMIB_DATA1N
HDMIB_D2BP
7
2
HDMIB_D2BP_M
7
2
HDMIB_DATA2P
5VS
HDMIB_D2BN
8
1
HDMIB_D2BN_M
8
1
HDMIB_DATA2N
HDMIB_CLKBP
5
4
HDMIB_CLKBP_M
5
4
HDMIB_CLOCKP
HDMIB_CLKBN
6
3
HDMIB_CLKBN_M
6
3
HDMIB_CLOCKN
7
2
7
2
HDMIB_D0BP
HDMIB_D0BP_M
HDMIB_DATA0P
8
1
8
1
S
HDMIB_D0BN
HDMIB_D0BN_M
HDMIB_DATA0N
*0_8P4R_04_SHORT
* 0_8P4R_04_SHORT
RN18
RN20
D 04
W/O level shift
W/O level shift
5VS_CRT
5VS
[16]
DAC_RED
D2
[16]
DAC_GREEN
[16]
DAC_BLUE
C
A
RB751S-40C2
R481
R482
2.2K_04
2.2K_04
9
DDCDATA
12
DDCLK
14
CRT_HSY NC
R335
0_04
HSY NC
Noise
16
CRT_VSY NC
R336
0_04
VSY NC
3
BLUE
4
GRN
5
RED
6
GND
W/O level shift
3.3VS
5VS_HDMI
12/ 15
D 04
R40
1M_04
2
Q39A
MTDK5S6R
R41
R42
HDMI_CTRLCLK
1
6
HDMIB_EXT1_SCL
5
Q39B
4
3
HDMI_CTRLDATA
MTDK5S6R
HDMIB_EXT1_SDA
HDMIB_EXT1_SCL
Q9
HDMIB_EXT1_SDA
2SK3018S3
PORTC_HPD
S
D
HDMI_HPD-C
HDMI_HPD-C
3.3VS
5VS_HDMI
5VS
D3
C
A
R43
1_04
5VS_HDMI_I N
RB551V-30S2
J_HDMI1
D 04
C68
C76
*10u_10V_Y 5V_08
10u_10V_Y 5V_08
19
HDMI_HPD-C
HOT PLUG DETECT
18
+5V
17
16
DDC/CEC GND
HDMI B_EXT1_SDA
SDA
15
HDMIB_EXT1_SCL
SCL
CLOSE TO J_HDM I1
14
RESERVED
13
HDMI_CEC
CEC
TMDS_CLOCK#
12
R54
*20m il_04
TMDS CLOCK-
11
10
CLK SHIELD
R51
*20m il_04
TMDS_CLOCK
TMDS CLOCK+
9
TMDS_DATA0#
TMDS DATA0-
8
SHIELD0
7
TMDS_DATA0
TMDS DATA0+
TMDS_DATA1#
6
R64
*20m il_04
TMDS DATA1-
5
4
SHIELD1
R60
*20m il_04
TMDS_DATA1
TMDS DATA1+
3
TMDS_DATA2#
TMDS DATA2-
2
SHIELD2
1
TMDS_DATA2
TMDS DATA2+
D 04
12/27
C12817-119A5-L
PCB Footprint = SK-C12841B
D
HMDI_INTEL
Q13
HMDI_INTEL
6-21-14A10-019
2SK3018S3
W/O level shift
J_CRT1
6-19-31001-266
108AH15FST01N1CC
PCB Footprint = C-108AH15X
RED
1
Nois e
L5
0_04
L6
FCM1005MF-600T01
2
L4
0_04
L3
FCM1005MF-600T01
GRN
L2
0_04
L1
FCM1005MF-600T01
BLUE
3
4
5
6
7
8
[3,9,10,11,13,14,15, 16,17,18,19,20,23,24,25,27,28,29,30,31,36]
3.3VS
[13,19,20,25,29,30,31,36]
5VS
Schematic Diagrams
For ESD
RD3
RD2
RD1
* BAV99 RECTIFIER
* BAV99 RECTIF IER
*BAV99 RECTIFIER
Sheet 12 of 42
HDMI, CRT
D 04
CLOSE TO J_HDM I1
R58
* 20m il_04
HDMI B_DATA0N
R56
* 20m il_04
HDMI B_DATA0P
R70
* 20m il_04
HDMI B_DATA2N
R68
* 20m il_04
HDMI B_DATA2P
6-20-14X30-115
9
10
11
12
DDCDATA
13
HSY NC
14
VSYNC
15
DDCLK
HDMI, CRT B - 13
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