National Instruments PXI Express PXIe-1085 Series User Manual page 21

Chapter 1 Getting Started
on this pin, the backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 signals to this external clock and distributes these signals to the slots. Refer to
Appendix A, Specifications, for the specification information for an external clock provided on
the PXI_CLK10_IN pin of the system timing slot.
You also can drive a 10 MHz clock on the 10 MHz REF IN connector on the front panel of
the chassis. When a 10 MHz clock is detected on this connector, the backplane automatically
phase-locks the PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 signals to this external
clock and distributes these signals to the slots. Refer to Appendix A, Specifications, for the
specification information for an external clock provided on the 10 MHz REF IN connector on
the front panel of the chassis.
If the 10 MHz clock is present on both the PXI_CLK10_IN pin of the System Timing Slot and
the 10 MHz REF IN connector on the front of the chassis, the signal on the System Timing Slot
is selected. Refer to Table 1-2 which explains how the 10 MHz clocks are selected by the
backplane.
Table 1-2. Backplane External Clock Input Truth Table
System Timing Slot Front Chassis Panel
PXI_CLK10_IN
No clock present No clock present
No clock present 10 MHz clock present
10 MHz clock present No clock present
10 MHz clock present 10 MHz clock present
A copy of the backplane's PXI_CLK10 is exported to the 10 MHz REF OUT connector on the
front panel of the chassis. This clock is driven by an independent buffer. Refer to Appendix A,
Specifications, for the specification information for the 10 MHz REF OUT signal on the front
panel of the chassis.
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Backplane PXI_CLK10,
10 MHz REF IN PXIe_CLK100 and PXIe_SYNC100
Backplane generates its own clocks
PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
Front Chassis Panel—10 MHz REF IN
PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
System Timing Slot— PXI_CLK10_IN
PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
System Timing Slot—
PXI_CLK10__IN