Table 39: Lbo Register Description - Alcatel MTK-40131 Datasheet And User Manual

LBO register
This register controls various loop-back
modes, as well as the routing of the
GCI B channels to/from the physical

Table 39: LBO Register Description

Mode
Normal
Simplex loop B2
Simplex loop B1
Simplex loop B1 and B2
Duplex loopback
Reserved
Reserved
Swap mode
BnDown : GCI B channel n, Downstream direction
BnUp : GCI B channel n, Upstream direction
TX(m) : Analog 'transmit' signal (upstream direction), line m
RX(m) : Analog 'receive' signal (downstream direction), line m
Alarm Bits
- After initialisation (e.g. due to a hardware reset), the CODSP itself will make the upstream CI/Alarm bit
active, and set the AlarmReg with an InitRequest value (i.e. "1xx"); the CI/Alarm bit will remain active
until the InitRequest is cleared by the GCI supervisor (indicating that the supervisor has done the necessary
re-initialisation of system parameters).
- In order to check the contents of the AlarmReg, execute the following GCI command:
ReadRequest ( MemId=2, Add=0x0010 );
This results in a 4 nibble value, e.g. "0xabgd", read by the supervisor.
- In order to clear the InitRequest alarm, in principle one must only clear one bit.
Therefore the supervisor should execute the following commands:
NewValue = "0xabgd" AND "0xFFFB";
WriteRequest ( MemId=2, Add=0x0010, NewValue );
- Note that the other bits in the alarm register are updated by the DSP at a 8kHz rate, and that they
are only used by the GCI supervisor; therefore the other bits might also be overwritten for one cycle,
clearing all bits (inclusive the InitRequest bit) in one command:
WriteRequest ( MemId=2, Add=0x0010, 0x0000 );
line analog channels. The bits are
codes as follows:
D2 D1 D0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
MTK-40131
GCI side
TX(0) -> B1Up
TX(1) -> B2Up
TX(0) -> B1Up
B2Down -> B2Up
B1Down -> B1Up
TX(1) -> B2Up
B1Down -> B1Up
B2Down -> B2Up
B2Down -> B1Up
B1Down -> B2Up
TX(0) -> B2Up
TX(1) -> B1Up
46
Analog side
B1Down -> RX(0)
B2Down -> RX(1)
B1Down -> RX(0)
TX(1) -> RX(1)
TX(0) -> RX(0)
B2Down -> RX(1)
TX(0) -> RX(0)
TX(1) -> RX(1)
TX(0) -> RX(1)
TX(1) -> RX(0)
B1Down -> RX(1)
B2Down -> RX(0)