Alcatel MTC-20172 Manuals

Manuals and User Guides for Alcatel MTC-20172. We have 1 Alcatel MTC-20172 manual available for free PDF download: Reference Manual

Alcatel MTC-20172 Reference Manual (104 pages)

S Interface Circuit for ISDN (SIC)

Brand: Alcatel | Category: Recording Equipment | Size: 1.24 MB

Table of Contents
3
General Description
11
Fig. 1. Typical Application
11
Interface and Operation Overview
12
The Digital Interface
12
Fig. 2.1 Timing in Normal Mode
12
Fig. 2.2 Timing in V* Inverted Mode
12
Table 2.1 : Possible Mode Combinations
13
The So-INTERFACE - Functional Overview
14
Fig. 2.6 Point-To-Point Configuration
15
Fig. 2.7 Point-To-Multipoint Configuration
15
The MTC-20172 SIC Operation Summary
16
Fig. 2.8 Block Diagram
16
Test Modes Summary
17
Pin and Package Data
18
Package and Dimensions
18
Pin Allocation and Short Description
19
Table 3.1: Pin List and Description, 22 and 28 Pin Package
20
Input/Output Types in Function of the Modes
21
Table 3.2 : Input/Output Types in Function of the Modes
21
Values and Usage of the Pull-Up Devices
22
Device Marking
22
Functional Description
23
General Features
23
Compatibility
23
Improved Features
23
Overview of the Use of MTC-20172 SIC in the ISDN System
24
General Description of the S-BUS Interface
24
The GCI Interface
25
The Physical Organization of the GCI Bus
25
General Content of the GCI Bus
25
Fig. 4.2 Frame Structure GCI
25
Power-Down on GCI
26
GCI Clock-Synchronization in the ISDN Environment
26
Clock Speed
27
Power Saving / Deactivation of MTC-20172 SIC
27
MTC-20172 SIC Activation
28
MTC-20172 SIC Activation in NT Mode
28
MTC-20172 SIC Activation in te Mode
28
MTC-20172 SIC Activation in LT/S and LT/T Modes
28
Crystal Oscillator Operation
28
Modes of Operation
29
Functional Explanation of the Special Signals
32
Detailed Operational Description of the S-Bus Interface
33
General Characteristics
33
Transmission Rate
33
Frame Structure
33
Fig. 5.1 S Frame Structure
33
AMI S-Bus Coding (General in RX and TX)
34
Balance Bits
34
AMI Violations for Frame Synchronization
34
Frame Synchronization; Distance Rule
34
Frame Synchronization; Multiframing Exceptions
34
Fig. 5.2 S Coding with AMI
34
Synchronization Principles, with Adaptive Bit-Timing
35
Synchronization Principles, Fixed Bus Timing at NT/LT-S
35
Pulse Polarity in the S-Bus Frame
35
Transmitted Frames
36
S-BUS Transmitter Analog Blocks
37
Polarity
37
MTC-20172 SIC Drivers, External Transformer and Circuits
37
Ternary Drivers : High-Ohmic State When Not Powered
38
Ternary Driver: Compatibility and Evolution
38
S-Bus Transmitter Timing and Framing; Jitter
39
S-BUS Receiver: Analog Parts and Synchronization
39
Transformer and Other External Devices
39
Ternary S-Bus Receiver Polarity and Balanced Operation
39
Ternary Receivers: Impedance While Not Powered
40
Activity Detection
40
Sensitivity/Agc
40
MTC-20172 SIC RX Signal Dynamics and Detection at TE/LT-T
40
MTC-20172 SIC RX Signal Dynamics at NT/LT-S
40
MTC-20172 SIC RX Detection Levels at NT/LT-S
40
Filtering
41
RX Frame Sync and Bit-Sampling in NT/LT-S Short Bus Mode
41
Frame Synchronization Details in Adaptive Timing
41
RX Bit-Synchronization in TE/LT-T and NT/LT-S Adaptive Bus
41
Timing Relation between RX and TX on the S-BUS
43
S-Bus Transmitter Versus Receiver Delay in TE/LT-T Mode
43
S-Bus Receiver Versus Transmitter Delay in NT/LT-S Mode
43
Delay Trimming Via XTR4 Pin
43
More Delay Trimming
43
Frame Relation between GCI and S-INTERFACE
43
S-Bus Transmitter Bit and Frame Clock NT/LT-S
43
S-Bus Transmitter Clock and Frame in te Mode
44
Transmitter Clock and Frame in LT-T Mode
44
Fig. 5.5 GCI S-Bus Phase Relation te Mode, RDY & ECHO Pin
44
E-Channel Generation in NT/LT-S
45
E-Channel Generation in NT in STAR Configuration
45
E-Channel Generation in LT-S for HDLC Pooling
45
E-Channel Generation: Operational
45
D-Channel Access in TE/LT-T
46
Fig. 5.6 GCI S-Bus Phase Relation NT/LT-S Mode, DE/CEB Timing
46
D-Channel Access Working Principles for the MTC-20172 SIC
47
The D-Channel Access Controller (D-AC) Functions
47
Fig. 5.7 State Diagram of D-Channel Access Procedure
47
READY Signal
48
Anticipation and LAPD Fairness
48
RDY Pin and Bit Operation in Basic Modes
48
Timing and Operation in Extended
48
Illegal Messages from the HDLC
48
E-Channel to External-HDLC Device at te Position
49
D-Channel Access in NT/LT-S: TIC Protocol
49
Multiframing; S and Q Channel Functions
49
Compatibility with Older MIETEC MTC-2072 SIC
49
Multiframing Enabling
49
Functional Behaviour at the NT/LT-S
49
Functional Behaviour at TE/LT-T Side
50
Automatic S and Q Bit Interpretation
50
Multiframing and S-Bus Synchronization
50
Ber Pin
50
Table 5.1 : Multiframing Sequence
50
The GCI Interface
51
General Content of the GCI Bus for the MTC-20172 SIC
51
The Physical Organization of the GCI BUS
51
Clock and Frame Signals (See Figure 9.2.)
51
Fig. 6.1 Relation of Clock, Frame and Data on the GCI Bus
51
Channel Selection
52
DATA Pin Tristate or Open Drain Operation
52
Power-Down and Power-Up on the GCI Bus
52
Fig. 6.1A Deactivation of the GCI Interface
52
Fig. 6.2 SDL Diagram NT
53
Fig. 6.3 SDL Diagram LT-S
54
Fig. 6.4 SDL Diagram TE, LT-T
55
The B-Channels on the GCI Bus
56
The D-Channels on the GCI Bus
56
The Command/Indication (C/I) Channel
56
Fig. 6.5 Explanation of Notation of the SDL Diagrams
56
General Information on the C/I State Diagrams
57
Fig. 6.6 SDL Diagram TE/LT-T, Unconditional States, Basic Mode
57
State Diagram for the NT Position
58
Fig. 6.7 Activation Sequence Outgoing Call
58
Fig. 6.8 Activation Sequence Incoming Call
59
State Diagram for the LT-S Position
60
State Diagram for the TE/LT-T Position
61
The Commands and Indications, Basic Mode
63
Commands and Indications Extended Mode
64
Table 6.2: Extended Mode Commands and Indications
64
C/I Equivalence Table
65
Command and Indications for NT Applications
66
Commands and Indications LT-S
67
Commands and Indications TE/LT-T
69
Fig. 6.10 SDL Diagram TE/LT-T, Unconditional States, Extended Mode
72
M-Channel + MX + MR : Physical Layer
73
M-Channel Activity
73
M-Channel Format, Bit and Byte Numbering Convention
73
Fig. 6.11 SDL Diagram of the M-Channel Receiver
73
Byte Transfer Procedure
74
Fig. 6.12 SDL Diagram of the M-Channel Transmitter
74
Fig. 6.13 Examples of Received M-Channel Messages
75
Comments on the MTC-20172 SIC M-Transceiver State Diagrams
76
M-Channel Messages and Registers
77
Introduction
77
M-Channel Receiver and Transmitter
77
General Content of M-Channel Messages
77
M-Channel, Basic Mode
77
S and Q Channel M-Channel Messages
77
S/Q M-Channel Messages, MTC-20172 SIC in NT/LT-S with Multiframing
77
S/Q M-Channel Messages, MTC-20172 SIC in TE/LT-T with Multiframing
77
S/Q M-Channel Messages, MTC-20172 SIC Multiframing Disabled
78
Internal Register M-Channel Messages
78
Write Operation
78
READ Operation and CONTENT Message
78
Detailed Bitmap of the Internal Registers
79
Identification Register; READ Only; Address 0H
79
Version Number Register; READ Only; Address 1H
79
Configuration Register; WRITE and READ; Address 2H
79
Table 7.1: Register Bitmap of MTC-20172 SIC
79
Output Register; WRITE and READ; Address 3H
80
IN1 and IN2 Registers; READ Only; Address 4H and 5H
80
Performance Register; READ Only; Address 6H
80
M-Channel Operation Messages Overview
81
Reset of the M-Channel Transceiver
81
Table 7.2: M-Channel Message Overview
81
Loops, Test Modes, System Tests
82
Wafer Test of the Device
82
Packaged Device Test
82
Equipment Tests, ISDN LOOP Tests, Acceptance Test
82
Test of the Device on the Assembled DSP Board
82
ISDN Loops and Other Tests of the Complete Equipment
82
System Tests, for Characterization of All Modes
83
PLL and Dplls
83
State Machines of the C/I Codes
83
M-Channel
83
D-Channel Access Protocol
83
Echo Channel and Echo Bus
83
S-Bus Receiver
83
S-Bus Input to Output (TE/LT-T)
83
Power-Down in NT and te
83
Power-Up in NT and te
83
Electrical, Physical and Environmental Specifications
84
Limiting Capabilities
84
Transient Energy Capabilities: ESD and LATCH-UP
84
Thermal Data
84
Recommended Electrical Operating Conditions
84
Static Characteristics
85
Power Supply
85
Static Characteristics of Digital Inputs
85
Table 9.1: Static Characteristics of the Power Supply
85
Table 9.2: Static Electrical Characteristics, Digital Inputs
85
Static Characteristics of Digital Outputs
86
Static Characteristics of Analog S-Bus Inputs
86
Table 9.3: Static Electrical Characteristics, Pull-Up Resistors
86
Table 9.4: Static Electrical Characteristics, Outputs
86
Static Characteristics of Analog S-Bus Outputs
87
Dynamic Characteristics
87
Master Clock
87
Table 9.6: Static Characteristics of the S-Bus Outputs
87
Table 9.7: Dynamic Characteristics of the Master Clock
87
DCL Output Clock (TE) and Other Derived Clock Signals
88
Fig. 9.1 Pulse Form of the 7.68 Mhz Clock
88
Table 9.8: Dynamic Characteristics of Derived Clock Signals
88
Serial GCI Interfaces
89
Fig. 9.2 GCI Timing Parameters in te
89
Table 9.9: Characteristics of GCI Signals, Master Modes
89
Fig. 9.3 GCI Timing Parameters in NT, LT-S and LT-T Mode
90
Table 9.10: Characteristics of GCI Frame, Slave Modes
90
RDY Pin
91
ECHO Pin
91
RSTB Pins
91
CEB Bus Timing
91
BER Pin
91
TM1-, TM2-, SCZ-, SSZ- Pins
91
The AUX Pins Used as General Purpose I/O
91
Table 9.11: Characteristics of GCI Data, Slave Modes
91
Quality and Reliability Specification
92
Quality
92
Product Acceptance Tests
92
Lot-By-Lot Acceptance Test
92
Assembly Monitor
92
Table 10.1: Acceptance Criteria
92
Table 10.2 : Assembly Monitor
92
Delivery Lot Certification
93
Quality System
93
Reliability
93
The Intrinsic Failure Rate
93
External Stress Immunity
93
The Useful Life
93
Related Documents
94
Application Note : ETS-TM3 Qualification
95
Scope
95
External Circuit
95
ETS-TM3 Configuration Setup
95
Network Terminations(NT)
95
ETS-TM3 Terminal Equipments (TE,LTT)
95
Qualification Results
96
Transformer VAC ZKB505/105
96
Fig. 12.2 Output Pulse Template for 50Ω
96
Fig. 12.3 Output Pulse Template for 400Ω
97
Application Note Network Terminator
100
Scope
100
NT Mode with MTC20171 4B3T UIC
100
Schematic Diagram
100
Description
101
Requirement for the Input and Output Stage
102

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