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CODSP Clock Recovery
PLL
The CODSP device derives its internal
clocks from the GCI's DCL input by
means of a PLL. The PLL automatically
detects the clock mode in use, and sets
the multiplication factor accordingly.
The PLL loop filter requires an external
capacitor as shown in the application
schematic.
Rfeed
AW
Rfeed
BW
SPICK
(Line 0)
or
SPICS
(Line 1)
Fig 13: Application suggestion for Semi-unbalanced ringing injection.
User-Defined I/O Pins
The pins SPIDI, SPICS and SPICK are
part of an SPI port which is used by Alca-
tel Microelectronics during product evalu-
ation and testing. They are available to
the user, via the GCI, as output bits (e.g.
for driving small indicator LEDs). The pin
SPIDO is used as part of the power-up
and testing routines, and the behaviour
during power-up cannot be guaranteed.
It is therefore advised not to make use of
this pin for any other purposes. The out-
puts can source or sink a maximum of
4mA each.
nc
rly
47µF
+5V
rly
26
MTK-40131
Note: In order to support "semi-unba-
lanced ringing" (DC bias equal to VbatR
superimposed on the differential ringing
signal), two of these outputs will be
active high during the active ringing
period on each channel (SPICK for chan-
nel 0 and SPICS for channel 1). This can
be used to drive a relay via an external
NPN transistor as shown in fig 13.
protection
nc
rly
-VbatR
Test functions
Please contact Alcatel Microelectronics.
line
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