Appendix B. Memory Population Rules; Ddr5 Dimm Population Rules - Intel M50FCP2UR Integration And Service Manual

Intel® Server System M50FCP2UR System Integration and Service Guide
B.1

DDR5 DIMM Population Rules

Note: Although mixed DDR5 DRAM DIMM configurations are supported, Intel only performs platform
validation on systems that are configured with identical DIMMs installed.
The following memory population rules apply when installing DDR5 DIMMs:
• All DIMMs must be DDR5 DIMMs.
All DIMMs in a processor socket must have the same number of ranks (unless explicitly specified
•
otherwise)
Mixing rules:
•
o Mixing DDR5 DIMMs of different frequencies and latencies is not supported within or across
processors. If a mixed configuration is encountered, the BIOS attempts to operate at the highest
common frequency and the lowest latency possible.
o x4 and x8 width DIMMs cannot be mixed in the same channel or same processor socket.
o Mixing of DDR5 DIMM types (standard RDIMM, 3DS-RDIMM, 9x4 RDIMM) within or across
processors is not supported. This will lead to a Fatal Error Halt during Memory Initialization.
o Mixing vendors is supported for RDIMMs and 3DS RDIMMs.
o Ranks mixing is not supported on a channel, expect for Standard RDIMM 1 Rank +2 Rank
combination, when 16 DIMMS for processor socket is populated.
For a single DDR5 DIMM in a dual-slot channel, populate slot 1 (blue slot).
•
For multiple DDR5 DIMMs per channel:
•
o For RDIMM, 3DS-RDIMM, 9x4 RDIMM, always populate DIMMs with higher electrical loading in slot
1 (blue slot) followed by slot 2 (black slot).
Memory slots associated with a given processor are unavailable if the corresponding processor
•
socket is not populated.
Processor sockets are self-contained and autonomous. However, all memory subsystem support
•
(such as memory RAS and error management) in the BIOS Setup is applied commonly for each
installed processor.
• For best system performance, memory must be installed in all eight channels for each installed
processor.
• For best system performance in dual processor configurations, installed DDR5 DIMM type and
population for DDR5 DIMMs configured to CPU 1 must match DDR5 DIMM type and population
configured to CPU 0.

Appendix B. Memory Population Rules

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