Intel 82562EZ Design Manual page 6

82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide
4.1.12 Ground Planes Under the Magnetics Module ........................................ 27
4.1.13 Non-Integrated Magnetics Modules and RJ-45 Connectors .................. 29
4.2 Layout for the 82562EZ(EX) PLC Device ........................................................... 30
4.2.1
4.2.2
4.3 Layout for the 82541xx Gigabit Ethernet Controller ............................................ 31
4.3.1
4.3.2
4.4 Physical Layer Conformance Testing ................................................................. 31
4.5 Troubleshooting Common Physical Layout Issues ............................................. 32
5.0 Design and Layout Checklists ...................................................................................... 35
6.0 Ball Number to Signal Mapping with Population Options.......................................... 37
7.0 Dual Footprint Reference Schematic ........................................................................... 45
A Measuring LAN Reference Frequency Using a Frequency Counter ......................... 53
A.1 Background ......................................................................................................... 53
A.2 Required Test Equipment ................................................................................... 53
A.3 Indirect Probing Method ...................................................................................... 54
A.4 Indirect Frequency Measurement and Frequency Accuracy Calculation Steps.. 55
A.5 Direct Probing Test Method, Applicable for Most 10/100 Devices (Devices that do
NOT support 1000Base-T)56
A.6 Direct Frequency Measurement and Frequency Accuracy Calculation Steps .... 57
B GigConf.exe Register Settings for 82541GI(EI) Devices ............................................ 59
Figures
1 ICH5 Platform LAN Connect Sections .................................................................. 3
2 Crystal Circuit........................................................................................................ 7
3 82562EZ(EX) LAN Disable Circuitry ................................................................... 11
4 82541xx LAN Disable Circuitry ........................................................................... 14
5 General Placement Distances............................................................................. 22
6 Trace Routing...................................................................................................... 24
7 Ground Plane Separation.................................................................................... 27
8 Ideal Ground Split Implementation...................................................................... 28
9 Termination Plane Example for
82562EZ(EX) PLC Device and Discrete Magnetics............................................ 30
10 82562EZ(EX) PLC Device Differential Signal Termination ................................. 31
11 Indirect Probing Setup......................................................................................... 54
12 Direct Probing Method ........................................................................................ 57
vi
Termination Resistors for Designs Based on 82562EZ(EX) PLC .......... 30
Light Emitting Diodes for Designs Based on 82562EZ(EX) PLC ........... 31
Termination Resistors for Designs Based on 82541xx .......................... 31
Light Emitting Diodes for Designs Based on 82541xx ........................... 31