Intel 82541PI Design Manual
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Intel 82541PI Design Manual

Intel 82541PI Design Manual

Dual footprint lom
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82541PI(ER) and 82562GZ(GX) Dual
Footprint LOM Design Guide
Application Note (AP-468)
Revision 2.1
April 2005

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Summary of Contents for Intel 82541PI

  • Page 1 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Application Note (AP-468) Revision 2.1 April 2005...
  • Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's Web site at http://www.intel.com.
  • Page 3 • Removed confidential status. • Added reference schematics. Feb 2005 • Added 82541PI(ER) board design and layout information to match reference schematics. • Removed 82562G(GT) Shrink Small Outline Package (SSOP) information. This information now resides in the 82562ET/GT/G LAN on Motherboard Design Guide.
  • Page 4 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Note: This page is intentionally left blank. Application Note (AP-468)

  • Page 5: Table Of Contents

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Contents Introduction ....................1 Scope ........................1 Terms ........................1 Reference Documents ..................... 2 Product Codes ......................2 82541PI(ER) Gigabit Ethernet Controllers ............... 2 82562GZ(GX) Platform LAN Connect (PLC) Devices..........3 1.6.1 Usage Modes ....................3 Frequency Control Device Design Considerations ......
  • Page 6 Designing with 82541PI(ER) Gigabit Controllers ........... 15 3.6.1 82541PI(ER) Gigabit Controller LAN Disable Guidelines......15 3.6.2 Power Supplies for 82541PI(ER) Gigabit Ethernet Controllers ....16 3.6.3 82541PI(ER) Controller Power Supply Filtering .......... 17 3.6.4 82541PI(ER) Controller Power Management and Wake Up ....... 17 3.6.5 82541PI(ER) Controller Test Capability ............
  • Page 7 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Light Emitting Diodes for Designs Based on 82541PI(ER) ........40 Schematic for EEPROM Footprints and LCI Connection........40 4.10 Termination of Unused Differential Signals on Gigabit Magnetics for 10/100 LOM Design ......41 4.10.1 Option 1: Board Level Stuffing ..............41 4.10.2 Option 2: Rework of Gigabit Magnetics............43...
  • Page 8 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Tables Product Ordering Codes................2 Drop-in Replacement Mode ................3 New Usage Modes ..................4 Recommended Crystals ................5 Crystal Parameters..................7 82562GZ(GX) Memory Layout (128B EEPROM)........14 82562GZ(GX) Memory Layout (512B EEPROM)........14 Recommended EEPROM Manufacturers ...........

  • Page 9: Introduction

    15 mm x 15 mm, 196-ball grid array package. Many of the critical signal pin locations on the 82541PI(ER) are identical to signals on the 82562GZ(GX) allowing designers to create a single design that accommodates these two parts.

  • Page 10: Reference Documents

    82562GZ 10/100 Mbps Platform LAN Connect (PLC) Datasheet. Intel Corporation. • 82562GX 10/100 Mbps Platform LAN Connect (PLC) Datasheet. Intel Corporation. • I/O Control Hub 5, 6 and 7 EEPROM Map and Programming Information. Intel Corporation. • Intel Packaging Databook, 1999. Intel Corporation (http://developer.intel.com/design/...

  • Page 11: 82562Gz(Gx) Platform Lan Connect (Plc) Devices

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide 82562GZ(GX) Platform LAN Connect (PLC) Devices ® Intel 82562GZ(GX) PLC devices use an I/O Control Hub (ICHx) that supports the PLC interface. In these designs, an 82562GZ(GX) PLC device is used in place of an 82562EZ(EX) PLC device.

  • Page 12: New Usage Modes

    Usability, reduced BOM cost, Strapping resistors, LAN Disable circuit except LED configuration C. and stronger Tx drive strength. and LED circuit design. See footnote 1. Only use this mode if advised to do so by an Intel representative. Application Note (AP-468)

  • Page 13: Frequency Control Device Design Considerations

    “Crystal Selection Parameters”. The Intel® Ethernet controllers also have bus clock input functionality, however a discussion of this feature is beyond the scope of this document, and will not be addressed. The chosen frequency control device vendor should be consulted early in the design cycle. Crystal and oscillator manufacturers familiar with networking equipment clock requirements may provide assistance in selecting an optimum, low-cost solution.

  • Page 14: Fixed Crystal Oscillator

    As clock routing can be difficult to accomplish, it is preferable to provide a separate crystal for each device. For Intel® Ethernet controllers, it is acceptable to overdrive the internal inverter by connecting a 25 MHz external oscillator to the X1 lead, leaving the X2 lead unconnected. The oscillator should be specified to drive CMOS logic levels, and the clock trace to the controller should be as short as possible.

  • Page 15: Ethernet Component Design Guidelines

    Ethernet Component Design Guidelines This section provides recommendations for selecting components and connecting special pins. The main design elements are the 82562GZ(GX) PLC device or the 82541PI(ER) Gagabit Ethernet controller, external resistor connections (82562GZ(GX) only), a magnetics module with RJ-45 connector, and a crystal clock source.
  • Page 16 MA-406H* Please consult with your Intel representative before implementing a design that uses another type of clock source. Careful design is required if using a fixed oscillator. Intel discourages the use of programmable oscillators and ceramic resonators. See Appendix A, “Measuring LAN Reference Frequency Using a Frequency Counter”...

  • Page 17: Crystal Circuit

    Figure 1 illustrates a simplified schematic of the 82562GZ(GX) and the 82541PI(ER) controller’s crystal circuit. The crystal and the capacitors form a feedback element for the internal inverting amplifier. This combination is called parallel-resonant, because it has positive reactance at the selected frequency.
  • Page 18 AT strips, rather than circular AT quartz blanks. Some crystal data sheets list crystals with a maximum drive level of 1 mW. However, Intel® Ethernet controllers drive crystals to a level less than the suggested 0.5 mW value. This parameter does not have much value for on-chip oscillator use.

  • Page 19: Reference Crystal

    10/100 and 10/100/1000Base-T Ethernet LAN, the transmitter reference frequency must be precise within ±50 ppm. Intel® recommends customers to use a transmitter reference frequency that is accurate to within ±30 ppm to account for variations in crystal accuracy due to crystal manufacturing tolerance.

  • Page 20: Temperature Changes

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Alternatively, a larger sample population of circuit boards can be used. A larger population will increase the probability of obtaining the full range of possible variations in dielectric thickness and the full range of variation in stray capacitance.

  • Page 21: Integrated Magnetics Module

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Integrated Magnetics Module The magnetics module has a critical effect on overall IEEE and emissions conformance. The device should meet the performance required for a design with reasonable margin to allow for manufacturing variation.

  • Page 22: Serial Eeprom For 82562Gz(Gx) Implementations

    EEPROM manufacturers. For details on the EEPROM, see the I/O Control Hub 5, 6, and 7 EEPROM Map and Programming Information. Note: See your Intel representative for later information on later versions of the I/O Control Hub. Table 6.

  • Page 23: Magnetics Modules For 82562Gz(Gx) Plc Devices

    82541PI(ER) Gigabit Controller LAN Disable Guidelines The 82541PI(ER) controller has a LAN disable function that is present on FLSH_SO, ball P9. This pin can be connected to a Super IO component to allow the BIOS to disable the Ethernet port (see Figure 3).

  • Page 24: Power Supplies For 82541Pi(Er) Gigabit Ethernet Controllers

    3.6.2 Power Supplies for 82541PI(ER) Gigabit Ethernet Controllers The 82541PI(ER) controller requires three power supplies: 1.2 V, 1.8 V, and 3.3 V. The 1.2 V supply must provide approximately 500 mA current, and the 1.8 V supply, approximately 230 mA current.

  • Page 25: 82541Pi(Er) Controller Power Supply Filtering

    LAN address filters must also be set. The initial power management settings are specified by EEPROM bits. When the 82541PI(ER) controller transitions to either of the D3 low power states, the 1.2 V, 1.8 V, and 3.3 V sources must continue to be supplied to the device. Otherwise, it will not be possible to use a wakeup mechanism.

  • Page 26: 82541Pi(Er) Controller Test Capability

    3.3 V Microwire* interface, serial EEPROM devices, with 64 x 16 (or 256 x 16) organization and a 1 MHz speed rating. The 82541PI(ER) EEPROM access algorithm drives extra pulses on the shift clock at the beginnings and ends of read and write cycles.

  • Page 27: Eeprom Map Information

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide SPI* EEPROMs that have been found to work satisfactorily with the 82541PI(ER) controller are listed in Table 11. SPI* EEPROMs must be rated for a clock rate of at least 2 MHz.
  • Page 28 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide ° Table 14. Electrical Specifications at 25 C for 10/100 Magnetics Insertion Loss (TX / RX) 0.1 through 0.999 MHz 1.0 dB maximum 1.0 through 15 MHz 0.35 dB maximum 15.1 through 6 0MHz 0.7 dB maximum...

  • Page 29: Oscillators For 82541Pi Controllers

    400 uH minimum 3.6.9 Oscillators for 82541PI Controllers The 82541PI clock input circuit is optimized for use with an external crystal. However, an oscillator may also be used in place of the crystal with the proper design considerations (see Table 17): •...

  • Page 30: 82541Pi(Er) Oscillator Solution

    Voltage Output Low (Vol) 20% VDD 3.6.10 82541PI(ER) Oscillator Solution There are two oscillator solutions for the 82541PI(ER): high voltage and low voltage. 3.6.10.1 High Voltage Solution (VDD = 3.3 V) This solution involves capacitor C1, which forms a capacitor divider with C of about 20 pF.

  • Page 31: 82541Pi(Er) Recommended Oscillators

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide 3.6.10.2 Low Voltage Solution (VDD = 1.8 V) The low voltage solution is similar to the high voltage solution. However, the low voltage includes a low consumption and low jitter clock oscillator that uses a 1.8 V external power supply. In this case, C1 will require adjusting according to the stray capacitance from X1.
  • Page 32 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Note: This page intentionally left blank. Application Note (AP-468)

  • Page 33: General Layout Considerations For Ethernet Controllers

    4). For example, separate them by 35 mils on a 7 mil thick prepreg. Designing for Gigabit operation is very similar to designing for 10/100 Mbps. For the 82541PI(ER) controller, system level tests should be performed at all three speeds.

  • Page 34: Crystals

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Figure 4. General Placement Distances Integrated Keep Ethernet controller and traces at least 1 inch from RJ-45 edge of PB (2 inches is preferred) w/LAN Magnetics Keep Ethernet controller 1 to 4 inches from LAN...

  • Page 35: Critical Dimensions For Discrete Magnetics Module And Rj-45

    Critical Dimensions for Discrete Magnetics Module and RJ- There are four critical dimensions that must be considered during the layout phase of an 82541PI(ER) and 82562GZ(GX) LOM implementation. These dimensions are identified in Figure 5 as A, B, C, and D.

  • Page 36: Distance B: Phy To Magnetics (Priority 2)

    4.2.3.2 PCI Interface for the 82541PI(ER) The PCI bus on 82541PI(ER) meets PCI 2.3 specification and operate as PCI slave devices for configuration and register programming. After the controllers have been properly initialized, they can also operate as PCI masters to fetch memory descriptors and to read/write data buffers.

  • Page 37: Critical Dimensions For An Integrated Magnetics Module

    Distance B: Ethernet Controller to Chipset For LCI on 82562GZ(GX) devices, the maximum length should be less than 10 inches on an ICH5, ICH6, or ICH7 platform. For the PCI bus on 82541PI(ER) controllers, the bus routing should meet PCI specifications.

  • Page 38: Corner Trace Routing

    Keep the signal trace lengths within a differential pair equal to each other. — For the 82541PI, do not use serpentines to try to match trace lengths in the differential pair. Serpentines cause impedance variations causing signal reflections, which can be a source of signal distortion.

  • Page 39: Signal Trace Geometry

    The reference plane for the differential pairs should be continuous and low impedance. It is recommended that the reference plane be ground (or 1.8 V, the voltage used by the 82541PI PHY). This provides an adequate return path for high frequency noise currents.

  • Page 40: Impedance Discontinuities

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide 4.4.2 Impedance Discontinuities Impedance discontinuities cause unwanted signal reflections. Avoid vias (signal through holes) and other transmission line irregularities. If vias must be used, a reasonable budget is two per differential trace. Unused pads and stub traces should also be avoided.

  • Page 41: Power And Ground Planes

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Some rules to follow for signal isolation: • Separate and group signals by function on separate layers if possible. Maintain a gap of 5 times the distance to the reference plane between all differential pairs (Ethernet) and other nets, but group associated differential pairs together.

  • Page 42: Ground Planes Under A Discrete Magnetics Module

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide 4.4.7 Ground Planes Under a Discrete Magnetics Module The magnetics module’s chassis or output ground (secondary side of transformer) should be separated from the digital or input ground (primary side) by a physical separation of 100 mils minimum.

  • Page 43: Ideal Ground Split Implementation (For Integrated Rj-45 Without Usb)

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Figure 9. Ideal Ground Split Implementation (for Integrated RJ-45 without USB) Board Edge RJ/Mag. Chassis RJ Shield Capacitor Capacitor connected Stuffing Stuffing to Chassis Options Options Digital Resistive Terminations LAN IC The table below gives some starting values for these capacitors.

  • Page 44: Non-Integrated Magnetics Modules/Rj-45 Connectors

    For the 82541PI, the 75 termination resistors are required to terminate the common mode of the twisted pairs that behave as a transmission line. These resistors help ensure that emissiion requirements are met.

  • Page 45: 82562Gz(Gx) Layout

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide 4.4.9 82562GZ(GX) Layout Guidelines (Routing LAN 3.3 V When Using a Copper Trace) When 3.3 V for the LAN device is NOT supplied by a solid copper power plane, then it becomes more important to make sure the power source will not carry system noise to the LAN device, and to ensure that the power trace does not restrict current flow to the LAN device.

  • Page 46: 82562Gz(Gx) Signal Terminations

    -2.35 mVpk to -2.55 mVpk for the negative peak and +2.35 mVpk to +2.55 mVpk for the positive peak. The RBIAS values previously listed should be considered starting values. Intel recommends that board designers measure each of their PCB’s output amplitude and then adjust the RBIAS values as required.

  • Page 47: Termination Plane

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Figure 13. Termination Resistors Placement (Integrated Magnetics Solution) 4.5.1 Termination Plane Resistors are used to terminate noise from the unused inputs of both the RJ45 connector and the magnetics module to the termination plane. The netname “termplane” is provided as a guide to the termination plane.

  • Page 48: 82541Pi(Er) Signal Terminations

    The four differential pairs are terminated with 49.9 Ω (1% tolerance) resistors, placed near the 82541PI(ER) controller. One resistor connects to the MDI+ (MDI positive) signal trace and another resistor connects to the MDI- (MDI negative) signal trace. The opposite ends of the resistors, using a wide trace, connect together and to ground through a single 0.1 µF capacitor.

  • Page 49: Termination Of Unused Differential Signals On Gigabit Magnetics For 10/100 Lom Design

    The three sections that follow provide the remedies for this issue. 4.10.1 Option 1: Board Level Stuffing 1. Layout resistor footprints on the pairs three and four of the differential traces for 82541PI(ER) LOM design. Refer to Figure 2. Possibly rework the magnetics module for 10/100 to be footprint compatible with the magnetics for gigabit.

  • Page 50: Typical Magnetics For Gigabit Lan Controller With Optional Resistors Footprint

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide 3. Replace the magnetics for the 82541PI(ER) with the one for the 82562GZ(GX) and then populate R1/R2 and R3/R4 for an 82562GZ(GX) LOM design. Refer to Figure Pin_1 Pin_2 ADCT AXCT Pin_3...

  • Page 51: Option 2: Rework Of Gigabit Magnetics

    OEMs need to work with their magnetics vendors for this option. Intel is working with some magnetics vendors to standardize the pinout assignments on magnetics modules. Application Note (AP-468)

  • Page 52: Option 3: Integrated Magnetics Module For 10/100 Mbps And Gigabit

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Pin_1 Pin_2 ADCT AXCT Pin_3 Pin_6 BDCT BXCT Pin_4 Pin_5 Pin_7 Pin_8 Connector 10 / 100Base-T Magnetics Module, with two, added internal jumpers. Rw = Rx, and Ry = Rz Rw, Ry, Rx, & Rz may be any value between 0-ohms and 100-ohms Figure 18.

  • Page 53: Physical Layer Conformance Testing

    (10/100/1000 Mbps). 2. Output Amplitude, Rise and Fall Time (10/100 Mbps), Symmetry and Droop (1000 Mbps). For the 82541PI(ER) controller, use the appropriate PHY test waveform. 3. Return Loss. This test indicates proper impedance matching, measured through the RJ-45 connector back toward the magnetics module.

  • Page 54: Troubleshooting Common Physical Layout Issues

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide 4.12 Troubleshooting Common Physical Layout Issues The following is a list of common physical layer design and layout mistakes in LOM designs. 1. Unequal length of the two traces within a differential pair. Inequalities create common-mode noise and will distort the transmit or receive waveforms.

  • Page 55: Pin Number To Signal Mapping With Population Options

    Note that the 82541PI(ER) pin name in the 82541PI(ER) Datasheet/Design Guide is slightly different from the signal name on the reference schematics. The Datasheet/Design Guide signal names maintain consistency with the 64-bit gigabit controller naming conventions, while the schematic names follow the conventions used by our engineers on their design tools.
  • Page 56 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Table 18. Ball Number to Signal Mapping (Sheet 2 of 8) Population Options 82541ER 82541PI 82562GZ(GX) Ball 82541ER 82541PI 82562GZ(GX) Comments Name Name Name SMB_ALERT# 3.3 V SMB_ALERT# LAN_PWR_ GOOD LINK100# LED2/...
  • Page 57 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Table 18. Ball Number to Signal Mapping (Sheet 3 of 8) Population Options 82541ER 82541PI 82562GZ(GX) Ball 82541ER 82541PI 82562GZ(GX) Comments Name Name Name ISOL_EXEC May have LAN Disable logic connected to this signal for 82562GZ(GX).
  • Page 58 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Table 18. Ball Number to Signal Mapping (Sheet 4 of 8) Population Options 82541ER 82541PI 82562GZ(GX) Ball 82541ER 82541PI 82562GZ(GX) Comments Name Name Name AVSS AVSS AVSS = VSS MDI[2]+ MDI[2]+ Magnetics...
  • Page 59 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Table 18. Ball Number to Signal Mapping (Sheet 5 of 8) Population Options 82541ER 82541PI 82562GZ(GX) Ball 82541ER 82541PI 82562GZ(GX) Comments Name Name Name 1.2 V 1.2 V 3.3 V 1.2 V 1.2 V...
  • Page 60 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Table 18. Ball Number to Signal Mapping (Sheet 6 of 8) Population Options 82541ER 82541PI 82562GZ(GX) Ball 82541ER 82541PI 82562GZ(GX) Comments Name Name Name 1.2 V 1.2 V 3.3 V 1.2 V 1.2 V...
  • Page 61 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Table 18. Ball Number to Signal Mapping (Sheet 7 of 8) Population Options 82541ER 82541PI 82562GZ(GX) Ball 82541ER 82541PI 82562GZ(GX) Comments Name Name Name AD[13] AD[13] AD[13] AD[13] No stuff C/BE#[0] C/BE#[0]...
  • Page 62 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Table 18. Ball Number to Signal Mapping (Sheet 8 of 8) Population Options 82541ER 82541PI 82562GZ(GX) Ball 82541ER 82541PI 82562GZ(GX) Comments Name Name Name AD[6] AD[6] AD[6] AD[6] No stuff AD[3] AD[3]...

  • Page 63: Self-Review Checklist For Combined Footprint Lom

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Self-Review Checklist for Combined Footprint LOM A Portable Data Format (PDF) Self-Review Checklist for a Combined Footprint LOM is available to aid designers via: http://developer.intel.com Application Note (AP-468)
  • Page 64 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Note: This page intentionally left blank. Application Note (AP-468)

  • Page 65: Reference Schematics

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Reference Schematics Following are reference schematics for the 82541PI/ER and 82562GX/EX (Mode 0 and 1). Application Note (AP-468)
  • Page 66 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Application Note (AP-468)
  • Page 67 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Application Note (AP-468)
  • Page 68 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Application Note (AP-468)
  • Page 69 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Application Note (AP-468)
  • Page 70 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Application Note (AP-468)
  • Page 71 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Application Note (AP-468)
  • Page 72 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Application Note (AP-468)
  • Page 73 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Application Note (AP-468)
  • Page 74 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Application Note (AP-468)
  • Page 75 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Application Note (AP-468)
  • Page 76 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Note: This page intentionally left blank. Application Note (AP-468)

  • Page 77: A Measuring Lan Reference Frequency Using A Frequency Counter

    ±30 parts per million (ppm). Most Intel LAN devices will operate properly with a 25.000 MHz reference crystal, provided it meets the recommended requirements for frequency stability, equivalent series resistance at resonance (ESR), and load capacitance.

  • Page 78: Indirect Probing Setup

    Almost all Intel Ethernet controllers that support 1000BASE-T Ethernet can provide a buffered 125 MHz clock, which can be used for indirect probing of the transmitter reference clock. The buffered 125 MHz clock will be a 5X multiple of the crystal circuit’s reference frequency...
  • Page 79 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Indirect Frequency Measurement and Frequency Accuracy Calculation Steps 1. Make sure the system BIOS has the LAN controller enabled. 2. Connect the test equipment as shown in Figure 3. Using the appropriate controls for your model of high resolution digital counter, make sure it can display ~125.0000 MHz with at least four decimal places frequency resolution.
  • Page 80 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Example 2. Given: The measured averaged center frequency is 125.00087 MHz (or 125,000,870 Hertz). 125000870 125000000 – FrequencyAccuracy ppm ---------------------------------------------------------------- 6.96ppm ⁄ 125000000 1000000 Note: The following items should be noted for an ideal reference crystal on a typical printed circuit board.

  • Page 81: Direct Probing Method

    82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide Figure 20. Direct Probing Method Direct Frequency Measurement and Frequency Accuracy Calculation Steps 1. Make sure the system BIOS has the LAN controller enabled. 2. Connect the test equipment as shown in Figure 3.
  • Page 82 82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide – FrequencyAccuracy ppm ------------------------------- - ⁄ y 1000000 where x = Average measured frequency in Hertz and y = Ideal reference frequency in Hertz Example 3. Given: The measured averaged center frequency is 24.99963 MHz (or 24,999,630 Hertz).

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