Intel 82562EZ Design Manual page 50

82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide
Table 13. Ball Number to Signal Mapping (Sheet 6 of 8) (Continued)
82541xx
Ball 82540EP
Pin
Ref Pin Name
Name
K10 1.2 V 1.5 V
K11 1.2 V 1.5 V
K12 AVSS VSS
K13 3.3 V 3.3 V
K14 XTAL1 XTAL1
L1 AD[14] AD[14]
L2 AD[15] AD[15]
L3 C/BE#[1] C/BE#[1]
L4 1.2 V 1.5 V
L5 1.2 V 1.5 V
L6 VSS VSS
L7 RVSD_NC CLK_BYP#
L8 NC 2.5 V
L9 1.2 V 1.5 V
L10 1.2 V 1.5 V
L11 VSS VSS
L12 JTAG_TMS JTAG_TMS
L13 JTAG_TRST# JTAG_TRST#
L14 JTAG_TCK JTAG_TCK
M1 AD[11] AD[11]
M2 AD[12] AD[12]
M3 AD[13] AD[13]
M4 C/BE#[0] C/BE#[0]
M5 AD[5] AD[5]
M6 VSS VSS
M7 AD[1] AD[1]
M8 RVSD_NC CLK_VIEW
M9 FLSH_CE# FLSH_CE#
42
82562EZ
1 2
D K 82541xx
Pin Name
VCC X X 1.2 V
VCC X X 1.2 V
VSSP X X VSS
VCC X X 3.3 V
X1
NC X AD[14]
NC X AD[15]
NC X C/BE#[1]
3.3 V X X 1.2 V
3.3 V X X 1.2 V
VSS X X VSS
ADV10 X X NC
NC X 1.8V
3.3 V X X 1.2 V
3.3 V X X 1.2 V
VSS X X VSS
NC X NC
JTXD[1] X X LCI
JTXD[2] X X LCI
NC X AD[11]
NC X AD[12]
NC X AD[13]
NC X C/BE#[0]
NC X AD[5]
VSSA X X VSS
NC X AD[1]
NC X NC
NC X NC
Population Options
82540EP 82562EZ
1.5 V 3.3 V
1.5 V 3.3 V
VSS VSS
3.3 V 3.3 V
AD[14] AD[14]
AD[15] AD[15]
C/BE#[1] C/BE#[1]
1.5 V 3.3 V
1.5 V 3.3 V
VSS VSS
NC NC
2.5 V No stuff
1.5 V 3.3 V
1.5 V 3.3 V
VSS VSS
NC NC
LCI LCI
LCI LCI
AD[11] AD[11]
AD[12] AD[12]
AD[13] AD[13]
C/BE#[0] C/BE#[0]
AD[5] AD[5]
VSS VSS
AD[1] AD[1]
NC NC
NC NC
Comments
Core Power
Plane
Core Power
Plane
AVSS = VSSP
= VSS
VCCP = 3.3 V
Core Power
Plane
Core Power
Plane
VSSA = VSS
PHY Power
Plane
Core Power
Plane
Core Power
Plane
VSSP = VSS
ICH drives this
signal low.
TRST needs to
be grounded to
disable JTAG.
JTAG becomes
difficult to use.
ICH drives this
signal low. TCK
needs to be
biased. JTAG
becomes
difficult to use.
VSSA = VSS