Intel 82562EZ Design Manual page 41

82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide
8. Incorrect differential trace impedances. It is important to have approximately 100 Ω
impedance between the two traces within a differential pair. This becomes even more
important as the differential traces become longer. To calculate differential impedance, many
impedance calculators only multiply the single-ended impedance by two. This does not take
into account edge to edge capacitive coupling between the two traces or other edge effects.
When the two traces within a differential pair are kept close to each other, the edge coupling
can lower the effective differential impedance by 5 Ω to 20 Ω. Short traces will have fewer
problems if the differential impedance is slightly off target.
9. For 82562EZ(EX) PLC designs, use of capacitor that is too large between the transmit traces
or too much capacitance on the magnetics module's transmit center tap to ground. Using
capacitors more than a few picoFarads in either of these locations can slow the 100 Mbps rise
and fall time. This will also cause return loss to fail at higher frequencies and will degrade the
transmit BER performance. If capacitors are used, the total of all capacitors placed on the
transmit traces and the center tap should equal less than 22 pF.
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