Intel 82562EZ Design Manual page 52

82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide
Table 13. Ball Number to Signal Mapping (Sheet 8 of 8) (Continued)
82541xx
Ball 82540EP
Pin
Ref Pin Name
Name
P5 AD[3] AD[3]
P6 AD[2] AD[2]
P7 EECS EECS
P8 VSS VSS
P9 FLSH_SO/ FLSH_SO
LAN_DISABLE#
P10 EEDI EEDI
P11 CTRL12 CTRL15
P12 3.3 V 3.3 V
P13 SDP[1] SDP[1]
P14 NC NC
1. This column will be checked if the 82562EZ pin names are different from their 82540EP/82541xx counterparts.
2. This column will be checked if the 82562EZ signal is different from the 82540EP/82541xx AND the 82562EZ gets a connection.
44
82562EZ
1 2
D K 82541xx
Pin Name
NC X AD[3]
NC X AD[2]
NC X EECS
VSSA X X VSS
NC X LAN_EN
NC X EEDI
NC X Pwr Regulator
VCC X X 3.3 V
JRXD[0] X X LCI
NC NC
Population Options
82540EP 82562EZ
AD[3] AD[3]
AD[2] AD[2]
EECS EECS
VSS VSS
LAN_EN LAN_EN
EEDI EEDI
Pwr Regulator No stuff
3.3 V 3.3 V
LCI LCI
NC NC
Comments
If EE from ICH
and 82540EP
are shared, a
Ω
0 pop is
required
because ICH
drives this in
reset.
VSSA = VSS
Connect to
LAN Enable
signal
If desired, this
can be shorted
to the ICH
EEDI because
it is an input in
ICH in reset.
Connect to
PNP. Don't'
stuff PNP on
82562EZ(EX).
VCCP = 3.3 V
ICH expects
this signal to be
high or
undriven.