Intel 82562EZ Design Manual page 47

Table 13. Ball Number to Signal Mapping (Sheet 3 of 8) (Continued)
82541xx
Ball 82540EP
Pin
Ref Pin Name
Name
D12 CLKR_1.8V NC
D13 AVSS VSS
D14 IEEE_TEST- NC
E1 3.3 V 3.3 V
E2 VSS VSS
E3 AD[17] AD[17]
E4 RVSD_VSS VSS
E5 VSS VSS
E6 VSS VSS
E7 VSS VSS
E8 VSS VSS
E9 VSS VSS
E10 VSS VSS
E11 ANALOG_1.2V 1.5 V
E12 ANALOG_1.2V 1.5 V
E13 MD[1]+ MDI[1]+
E14 MDI[1]- MDI[1]-
F1 IRDY# IRDY#
F2 FRAME# FRAME#
F3 C/BE#[2] C/BE#[2]
F4 VSS VSS
F5 VSS VSS
F6 VSS VSS
F7 VSS VSS
F8 VSS VSS
F9 VSS VSS
F10 VSS VSS
F11 AVSS VSS
F12 NC PHY_TSTPT
82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide
82562EZ
1 2
D K 82541xx
Pin Name
ISOL_TI X X 1.8V
VSSA X X VSS
ISOL_TCK X X 2-pin header
3.3 V
VSS
NC X AD[17]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCCT X X 1.2 V
VCCT X X 1.2 V
RDP X X MDI
RDN X X MDI
NC X IRDY#
NC X FRAME#
NC X C/BE#[2]
VSSR X X VSS
VSSR X X VSS
VSS
VSS
VSS
VSS
VSS
VSS X X VSS
NC X NC
Population Options
82540EP 82562EZ
2.5 V No stuff
VSS VSS
NC NC
AD[17] AD[17]
1.5 V 3.3 V
1.5 V 3.3 V
MDI MDI
MDI MDI
IRDY# IRDY#
FRAME# FRAME#
C/BE#[2] C/BE#[2]
VSS VSS
VSS VSS
VSS VSS
NC NC
Comments
May have LAN
Disable logic
connected to
this signal for
82562EZ(EX).
AVSS = VSSA
= VSS
May have LAN
Disable logic
connected to
this signal for
82562EZ(EX).
Core Power
Plane
Core Power
Plane
Same signal -
different
names.
Same signal -
different
names.
VSSR = VSS
VSSR = VSS
AVSS = VSS
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