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82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide
3.3.5.2
82541PI (C0 Stepping) Oscillator Solution
There are two oscillator solutions for the 82541PI: high voltage and low voltage.
High Voltage Solution (VDD = 3.3 V)
This solution involves capacitor C1, which forms a capacitor divider with C
This attenuates the input clock amplitude and adjusts the clock oscillator load capacitance.
V
V
This enables load clock oscillators of 15 pF to be used. If the value of C
be adjusted by tuning the input clock amplitude to approximately 1 V
then C1 is 10 pF ±10%.
A low capacitance, high impedance probe (C < 1 pF, R > 500 K Ω) should be used for testing.
Probing the parameters can affect the measurement of the clock amplitude and cause errors in the
adjustment. A test should also be done after the probe has been removed for circuit operation.
If jitter performance is poor, a lower jitter clock oscillator can be implemented.
Low Voltage Solution (VDD = 1.8 V)
The low voltage solution is similar to the high voltage solution. However, the low voltage includes
a low consumption and low jitter clock oscillator that uses a 1.8 V external power supply. In this
case, C1 will require adjusting according to the stray capacitance from X1.
18
= VDD * (C1/(C1 + C
in
stray
= 3.3 * (C1/(C1 + C
in
stray
VDD=3.3
C1~10pF
Clk oscillator
Board Capacitance
Not a Component
VDD=1.8
C1~40pF
Clk oscillator
Board Capacitance
Not a Component
))
))
K14
X1
Cstray~20pF
K14
X1
Cstray~20pF
of about 20 pF.
stray
is unknown, C1 should
stray
. If C
equals 20 pF,
ptp
stray
Tabor
82541PI
C0 Step
Tabor
82541PI
C0 Step
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