Intel 82562EZ Design Manual page 3

Dual footprint
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Revision History
Revision
0.25
0.75
1.0
1.5
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide
Revision Date
Description
Aug 2002
Initial publication of preliminary design guide information.
Sep 2002
Revised Design Guide information.
Replaced reference design schematic.
Revised EEPROM map and bit descriptions.
Oct 2002
Revised Design Guide Information
Removed EEPROM information due to publication of separate guides.
Sep 2003
Published revised design guide information:
Added 82541GI coverage
Removed Confidential status
Updated schematics, removing redundant caps
Revised LAN disable circuit
Mar 2004
Published revised and updated design guide information:
Added information for the 82541PI
Updated schematics to include 82541PI
July 2004
Revised title for more clarification.
Oct 2004
Added crystal start-up information. Information includes:
New crystal parameters
Crystal selection guidelines
Crystal validation methods
Crystal testing methods
Added 82562EX applicability.
Added new values for TX and RX terminations (next to LAN silicon). New values are now
110 Ω for both TX and RX terminations.
Added new starting values for RBIAS100 and RBIAS10. New starting values are now 649
Ω for RBIAS100 and 619 Ω for RBIAS10.
Updated reference schematics to reflect new Tx and Rx termination values, new LAN
disable circuit, RBIAS100/RBIAS10 values, and VIO signaling connection and pullup
resistor value.
Change resistor value for pin A13 from 3.3K Ω to 1K Ω.
Nov 2004
Jan 2005
Changed text in the Catalyst EEPROM revision H table note from "Revision H or
higher not supported" to "Revision H is not supported".
Added a 0.01 µf capacitor between Ball C2 (M66EN) and ground to meet IEEE PCI
specification (sheet 2 of reference schematics).
Removed the Design and Layout Checklists. These checklists are now separate
Microsoft* Excel spreadsheets.
Jan 2005
Updated reference schematics to reflect current differential pair termination resistor values
for the 82541(PI/GI/EI) and 82540EP.
Updated section 4.2.1 "Termination Resistors for Designs Based on 82562EZ/EX PLC
Device" to reflect current resistor and RBIAS values.
Updated section 4.3.1 "Termination Resistors for Designs Based on 82541xx" to reflect
current resistor values.
Apr 2005
Added revision history to reference schematics.
Changed signal name SUPER_IO_GP to SUPER_IO_DISABLE on reference schematics
sheet 2.
June 2006
Removed 82540EP LAN disable note from Section 3.3.1.
June 2006
Added Pulse H5007 discrete magnetics reference to Table 10.
January 2008
Updated reference schematics: sheets 2 through 5.
Added link to Design and Board Layout Checklists in Section 5.0.
Added recommended crystals for the 82541PI.
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