Table of Contents
Advertisement
pins than the CPU would provide with all the external bus pins used. The
memory map for the Adr/IO switch ON mode is shown on the following figure:
(5) FPGA content version
7
Address:C2
H
Read/Write
The FPGA content version can be found in the PE "Help - About" dialog, when
the debugger is started.
(6) Mainboard version
7
Address:C3
H
Read/Write
• For the Mainboard v. 1.1, there is 11H in this register.
• For the Mainboard v. 1.2, there is 12H.
• For the Mainboard v. 1.3, there is 13H, and so on.
Not Available
Iimage of the area
FF4000-FFFFFF
Peripheral
External
6K
Int. RAM
External-FPGA
Peripheral
External bus mode with Adr/IO on
6
5
4
Xilinx content version
(R)
6
5
4
Mainboard version
(R)
77
77
77
77
FFFFFFH
100000H
00FFFFH
004000H
003900H
002000H
0018FFH
000100H
0000BFH
000000H
3
2
1
3
2
1
0
0
Advertisement
Table of Contents
