Table of Contents
Advertisement
M E M O R I E S
• There are four 128kx8 SRAM memory chips mounted on the board by
default, which makes 512kB in total. Optionally, 512kx8 SRAM memory
chips can be mounted on the board to extend the SRAM memory amount to
2MB.
• The MB29F008 FLASH memory provides 256kx8 or 128kx16 bits of
permanent memory. The selection between 8 and 16 bit access is done by
the FL8/16 DIP switch on the mainboard.
For the memory maps in selected CPU modes, see the "Mainboard
Programmer's Reference" chapter.
F P G A
FPGA integrates the biggest portion of the Mainboard functionality. It is a user
programmable HW chip, which can be reprogrammed unlimited number of
times. In fact, it is reprogrammed each time the power is applied to the board or
the Mainboard reset button is pressed. To change the FPGA configuration, the
IC9 FPGA EEPROM must be reprogrammed. This can be done by the FPGA
EEPROM programming tool.
For details about FPGA registers, see the "Mainboard Programmer's Reference"
chapter.
C A N
I N T E R F A C E S
There are two CAN interfaces – CAN0 and CAN1. The 82C250 chips are used
to interface the CPU CAN0 and CAN1 signals to a CAN network.
The P3, P4 potentiometers are used to control rise and fall slope of the CANH,
CANL signals and the standby mode of the 82C250 chip. To set the high-speed
mode of the 82C250 interface, set the P3 (P4) potentiometer to the rightmost
position (if you don't know the current position, just turn it 20-times clockwise).
To set the standby mode, set the potentiometer to the leftmost position. Setting
in between the 0.3-0.75 range of the potentiometer scale will set the value of
slope-limiting.
The default setting for the P3, P4 potentiometers is the rigtmost position (high-
speed mode).
U A R T
I N T E R F A C E S
There are three UART interfaces provided on the Mainboard – two for the
UART0, UART1 CPU signals and one for the User (FPGA) UART. The
UART0&1 interfaces do not support neither CTS/RTS, neither the DTR, DSR
signals. The User UART support RTS/CTS signals for the hardware flow
control. This allows communication on the highest possible baud rates.
48
48
48
48
Advertisement
Table of Contents
