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Mainboard reset button is pressed or power is removed and then applied
again to the board while J4 is SHORT, the FPGA will not be configured
so the Mainboard will not work properly. To return to the standard
configuration mode, J4 must be removed.
2. On the CPU board, check the J19, J20. Both of them must be ON. On
the mainboard, place two jumpers to the J11, J12 positions. This will
connect the I2C SCL, SDA lines to the FPGA EEPROM.
3. Or (instead of the step 2), use the FPGA EEPROM programming
register to program the EEPROM.
Warning: Although the EEPROM can't be erased by chance, because the
programming mode must be set by the J4 jumper, user is not supposed to access
this register. Instead, he/she should use the "FPGA EEPROM programming
tool". For availability of the tool, please check the Processor Expert WWW site.
(1) FPGA EEPROM programming register
This register is used by the FPGA EEPROM programming tool. Its
description here is included only for reference. Please, avoid writing to this
register - it can cause erasing of the FPGA EEPROM content and thus non-
functionality of the whole board.
FEPR[7:0]
7
Address: EF
SDAB
H
Read/Write
R/W
Initial Value
(1)
[Bit 7] SDAB: SDA line data bit
• Write
0: FPGA EEPROM SDA line is pulled to '0'
1: The FPGA EEPROM SDA line is released the the 'H' state (managed
by a 10k pullup)
• Read
The state of the SDA line is read out
[Bit 6] SCLB: SCL line data bit
• Write0
0: FPGA EEPROM SCL line is pulled to '0'
1: The FPGA EEPROM SCL line is released the the 'H' state (managed
by a 10k pullup)
• Read
The state of the SCL line is read out
[Bit 5] PEN: Programming enable
0: The programming is disabled even with the J4 jumper short.
1: If the J4 jumper is SHORT, the programming is enabled.
6
5
4
SCLK
PEN
---
B
R/W
R/W
---
(1)
(0)
(---)
72
72
72
72
3
2
1
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(---)
(---)
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0
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(---)
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