Fujitsu DevKit16 User Manual
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Fujitsu DevKit16 User Manual

Fujitsu DevKit16 User Manual

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FUJITSU MICROELECTRONICS EUROPE
Development tools for 16LX Family
User Guide
DevKit16
1.28
Version
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Summary of Contents for Fujitsu DevKit16

  • Page 1 1.28 Version Version Version Version FUJITSU MICROELECTRONICS EUROPE Development tools for 16LX Family DevKit16 User Guide...
  • Page 2 D E V E L O P M E N T T O O L S F O R 1 6 L X F A M I L Y DevKit16 User Guide...

  • Page 3: Table Of Contents

    Get it running ..........................16 (TM) Design application with Processor Expert and run it using Softune Workbench monitor debugger............................16 Run first application using Softune WorkBench and FUJITSU monitor debugger....16 (TM) Run first application using Processor Expert and its Debugger&Kernel ......17 Processor Expert tutorial......................19 Create your own tutorial (step by step)..................19...
  • Page 4 How to burn user program into the FLASH ................31 How to burn the SOFTUNE debug monitor................32 How to burn the PE debug kernel .....................33 How to burn the CPU FLASH without Devkit16..............34 Running burned program ......................35 FlashTool commands - parameters ...................35 Notes .............................35...
  • Page 5 Switches ............................53 Jumpers ............................55 The Mainboard Programmer‘s Reference ..................61 Register addresses and chip selects....................61 Interrupts .............................61 Simulated CPU ports (P0, P1, P2, P3 of Fujitsu FLASH CPU)..........62 Add-on FPGA ports ........................63 Add-on FPGA output-only port....................64 User UART...........................65 C ..............................67 Keyboard controller........................70 LED display ..........................71...

  • Page 6: What Is In This Guide

    - to get your results soon. You could print a copy of this document for further use, when you start work with the DevKit16 boards. DevKit16 provides a lot of features, so this guide introduces them using top- down approach. The guide describes how to use DevKit16 for the 16LX series MCU, allowing to get acquainted with the methods for developing and debugging 16LX-driven applications.

  • Page 7: What Is Not Included In This Guide

    G U I D E This guide is not detailed manual for the CPU, parts and software tools. Please find more in the following resources: MCU, Softune Workbench and tools – FUJITSU Micros CD ROM (Ver 3.0 or higher) (TM) Processor Expert and tools –...

  • Page 8: What Is Included In Devkit16

    Chapter What is included in DevKit16 Brief overview of what you’ll find inside DevKit16 package DevKit16 package contains both HW boards and SW tools on CD. H A R D W A R E The DevKit16 HW includes • CPU personality board (default for MB90F543 MCU) •...
  • Page 9 • Fujitsu Monitor Debugger for MB90F543 to provide debug for Softune on DevKit16 • (TM) Processor Expert • Bean Wizard • (TM) Processor Expert Debug Kernel for MB90F543 • DevKit16 FLASH Programming tool 7 7 7 7...

  • Page 10: Devkit16 Features And Technical Specification

    This chapter introduces features of DevKit16 and provides necessary technical and operational information for DevKit16. he FUJITSU DevKit16 concentrates the combination of five most requested HW development kits features: C O M B O F E A T U R E S •...

  • Page 11: Open Hw Architecture

    • provides large RAM and FLASH with fast download and programming • provides additional peripheral devices – PC keyboard interface, EEPROM, LED Display, I • Optional low level HW debug support (breakpoints, trace) O P E N A R C H I T E C T U R E •...

  • Page 12: Getting Started

    SW installation. evKit16 is designed as a low cost but highly functional development platform for FUJITSU 16LX MCU family. It is not a high end emulator but it provides significant advantages for MCUs with External Bus Interface. In combination with powerful software tools including debuggers it provides enough capacity for fast application development.

  • Page 13: Default Settings For Softune

    How to... When this step went OK, switch power off and connect DevKit16 with PC using attached cable to USER (FPGA) UART and a free serial port on PC, which is not used by other device in PC.

  • Page 14: Default Settings For Processor Expert(Tm)

    J1 (serial line reset polarity selection) must be in the 1-2 position for Softune, but in the 2-3 position for PE. Serial line reset is used for remote reset of DevKit16 by both environments.
  • Page 15 21 such resources, which you can choose using TimerInt property Timer according to the required timing parameters and accuracy in property Interrupt period. If you need functionality, you can choose appropriate bean and PE offers the possible MCU resources Figure: Selecting a CPU timing resource for the TimerInt bean Figure: Setting the interrupt period of the TimerInt bean...
  • Page 16 – and build application using classic tools (select Tools | Make from the main menu) – compiler, assembler, load to DevKit16, debug it before final burn-in – these are typical steps when working (TM)

  • Page 17: Sw Installation

    Each software – Softune and Processor Expert has its own installation. You should find 16bit tools full installation on FUJITSU Softune CD and run its setup.exe. On DevKit16 CD choose directory “Install” and run setup.exe. Installation will navigate you, for documentation reading you need to install also...

  • Page 18: Get It Running

    Processor Expert kernel or other program burned in the Mainboard FLASH. In such a case, you must burn the Fujitsu debug monitor into the Devkit16 - please refer to the chapter 6 (Flash It), paragraph “How to burn Fujitsu debug monitor”.

  • Page 19: Run First Application Using Processor Expert

    16LX family including (TM) high speed (115200Bd) download, we need to burn Processor Expert Debug Kernel to DevKit16 Main board FLASH instead of Fujitsu Monitor Debugger. (TM) In Processor Expert choose Tools | Burn PE Debug Kernel IR. This will run DevKit16 FLASH Programming tool with correct parameters in Auto program mode.
  • Page 20 Now you should change Main board System configuration DIP switch as follows: • setting for CPU external bus mode, FLASH in UMB Now, load the „Demo.LEDs“ project in Processor Expert. Check if there is no reported error after project loads, press F9 shortcut key, which starts codesign, builds the project and starts the debugger.

  • Page 21: Processor Expert Tutorial

    Tutorial project for Processor Expert and DevKit16 is located in directory . This demo project ProcessorExpert\Projects\Demo.Tutorial\LED.pe contains two BitIO beans connected to LEDs on DevKit16 and ExtInt bean connected on INT2. The LEDs are toggled on external interrupt. The interrupt is generated by the PC keyboard.
  • Page 22 Direction Output Init. Value The only one generated method : NegVal Note: DevKit16 contains only red LEDs conntected to the I/O ports of the CPU. Do not be confused from the name of the bean. ExtInt: Bean name Button Pin for I/O...
  • Page 23 Processor Expert saves all files automatically. • Debug . Check the settings of jumpers on the DevKit16, connect your PC with your DevKit16 board using serial cable, connect power supply to DevKi16 and select command main menu | Debug | Start Debug. If you find any problem with initialization of the debugger please refer to debugger documentation: open Cpu Inspector - page Debugger and press F1.

  • Page 24: Application Debug

    Very experienced developers often use technique of their own monitoring of running program behavior using character oriented (display) device. This approach is also supported by DevKit16 and optional VGA graphic card, which allows connect standard VGA display to DevKit16 and provides fast buffered access (much faster than serial line).

  • Page 25: Benefits Of Devkit16 For Software Debugging

    S O F T W A R E D E B U G G I N G DevKit16 provides the same feature as high end emulator – application thinks, that works with single chip and runs program in ROM or FLASH, but in fact the program is running in Main board RAM in final address space under software debugger control or as standalone.

  • Page 26: Softune Workbench And Fujitsu Monitor Debugger

    F U J I T S U M O N I T O R D E B U G G E R The DevKit16 is equipped with its adaptation of Fujitsu Monitor Debugger. This adaptation features with: • Communication speed 9600Bd or 38400Bd •...

  • Page 27: Processor Expert (Tm) Debug Kernel Features

    P R O C E S S O R E X P E R T D E B U G K E R N E L F E A T U R E S ( T M ) (TM) Processor Expert provides extensive support of debugging with up to 256 „software“...
  • Page 28 • 9 – ROM Correction, INT9 • 10 – exception • 15 – external interrupt 0,1 • No more CPU resources are used in PE Debug kernel. • Breakpoints references are stored in Frontend. • For other information, please check help for the DevKit16 debugger.

  • Page 29: Flash It

    Chapter Flash It! The DevKit16 FLASH Programming Tool is a standalone tool that can be used to program both the external FLASH (256kB) located on the Mainboard and internal FLASH (128kB) provided by the MB90F543 CPU. O V E R V I E W...

  • Page 30: Installing The Flash Programming Tool

    T O O L From within the Processor Expert environment, application can be easily burned into the FLASH - just click on the Tools | Fujitsu DevKit16 Flash Programming. The FLASH Programming Tool will be run in an non- interactive mode, with PE setting all the necessary parameters automatically.
  • Page 31 – CPU (internal FLASH), Main board (external FLASH) or both (internal & external FLASH) COM Port – Select the right COM port where you have a serial cable for communication with DevKit16. CPU Frequency – Select the actual CPU crystal oscillator frequency. This determines the speed of serial communication.

  • Page 32: Commonly Used Settings Of The Controls

    Flashtool prior to the 1.2, you can download the latest Flashtool installation package from the PE Web site. • If you use standard Devkit16 (CPU board in connection with Mainboard) without any additional HW, that could cause the AD bus contention, set the “External bus free”...

  • Page 33: Necessary Devkit16 Mainboard Hw Settings

    E.g., when burning Fujitsu debug monitor or PE debug kernel, select the “Base address FC0000” option. Note: special care must be taken when burning a mixed mode application. In mixed mode, both internal and external FLASH memories are accessible in the MCU memory space. With the “external FLASH 200BC - Base address FC0000”...

  • Page 34: How To Burn The Softune Debug Monitor

    , where xxx is the CPU type) uses only 9600 Bd. SoftuneMonitor9600_xxx.abi When using the 38400 Bd variant, the Devkit16 UART must be configured for RTS/CTS hardware flow control mode (J9 must be in the 2-3 position), otherwise some data can be lost during the communication. To burn the Softune debug monitor to the Devkit16 external FLASH, follow these steps: 1.

  • Page 35: How To Burn The Pe Debug Kernel

    (internal RAM) variant of the PE debug kernel. To burn the PE debug kernel to the Devkit16 external FLASH, follow these steps: 1.

  • Page 36: How To Burn The Cpu Flash Without Devkit16

    The Flashtool also allows burning the CPU internal FLASH without the need for using the Devkit16 Mainboard. This is important in the moment when you have an application board of your own and you want to verify if the application you have written is working well on your board.

  • Page 37: Running Burned Program

    FLASH. N O T E S For more details about: DevKit16 memory, I/O mapping and simulated ports see the chapter “Mainboard Programmer’s Reference” CPU modes and hardwired vector in external FLASH see the CPU documentation.

  • Page 38: Error Messages

    Set the right mode. Error in communication - disconnected cable, COM port occupied by another program, etc. MCU busy - the DevKit16 is busy and cannot download kernel into the RAM. Command error - the BI-Rom doesn‘t support downloading into the RAM...

  • Page 39: Processor Expert Beans Intflash And Extflash - Runtime Support Of Flash Access And Design Time Checks

    Debug already inited - internal error – the last communication wasn‘t closed correctly. Try to restart DevKit16 programming tool Not supported - not supported command – possible old version of kernel. No answer from kernel - kernel is not responding – try repeat programing cycle again Time out - kernel is not responding –...

  • Page 40: Cpu Board For Mb90F543 Description

    Chapter CPU board for MB90F543 description This chapter provides detailed description of CPU board for MB90F543 including all DIP switches, jumpers and connectors. For other CPU board types, please see the documentation supplied with them. CPU board can work standalone or in connection with the Main board. If the Main board is in use, please switch all switches on CPU board configuration DIP to OFF.

  • Page 41: Connectors

    • power supply connector for external power source Hi-speed crystal Device Bus Low-speed crystal RST & HST DC power supply CPU Pins CPU serial interface Jumpers DIP switches Interface Bus This part contains description of CPU board for MB90F543CPU. • Connectors •...
  • Page 42 J23 as well. K9: power supply connector Before applying the power to the Devkit16, check the polarity of your power chord plug – the GND must be in the center, while the +9V on the shell of the connector. Even thought the DevKit16 power lines are protected by a diode on the power input, do not ever apply power with the opposite polarity.
  • Page 43 K3, K4, K5, K6: CPU pins connectors A16 1 2 A17 INT6 31 32 INT7 A18 3 4 A19 ADTG 33 34 AVCC A20 5 6 A21 AVR+ 35 36 AVR- A22 7 8 A23 AVss 37 38 AN0 ALE 9 10 #RD AN1 39 40 AN2...

  • Page 44: Jumpers, Buttons And Switches

    J11: GND connector 1: GND 2: GND 3: GND 4: GND 5: GND 6: GND J U M P E R S , B U T T O N S A N D S W I T C H E S J13: Supply for the whole board When SHORT, the +5V from the voltage regulator is connected to board VCC.
  • Page 45 Warning: if you want to use the K7 connector when Mainboard is connected to the CPU board, you have to disconnect the selected serial interface (UART0 or UART1) from the RS232 drivers on the Mainboard. To achieve this, remove jumpers on positions 3-4, 5-6 from both the J21 and J22 headers on the Mainboard.
  • Page 46 These switches should be used only when using the CPU board without Mainboard, or with the FPGA disabled (see the description of J29 in the Mainboard section). 1:MD0, 2:MD1, 3:MD2 – these switches are connected to CPU pins MD0, MD1, MD2. In the ON position, a switch pulls the signal connected to it to log ‘0’.

  • Page 47: Default Jumper Settings

    8 7 6 5 4 3 2 1 Figure 1: CPU board layout and default jumper settings D E F A U L T J U M P E R S E T T I N G S These jumpers come in the SHORT position as a default factory setting: J2: The CPU is connected to the +5V power supply through this jumper J3: The CPU AVCC supply pin is connected +5V power supply through this jumper J4: The CPU AGND supply pin is connected to the GND through this jumper...

  • Page 48: Main Board Description

    Chapter Main board description M A I N B O A R D O V E R V I E W The Mainboard contains these features: • 512K of additional RAM with 16bit access, 0 wait • 128K of additional FLASH with configurable 8/16 bit access, 0 wait •...
  • Page 49 • PC-AT keyboard interface with connector • Amplifier and speaker for sound generation using CPU periph. - sound generator or PPG • 8 test LEDs as in CAN100 board, custom FPGA status LED • LED for indication of RESET from RS232 •...

  • Page 50: Memories

    M E M O R I E S • There are four 128kx8 SRAM memory chips mounted on the board by default, which makes 512kB in total. Optionally, 512kx8 SRAM memory chips can be mounted on the board to extend the SRAM memory amount to 2MB.

  • Page 51: Led Diodes

    There are 11 LED diodes on the Mainboard: 8 of them are connected to the P4 CPU port in the same way as LEDs on the Fujitsu CAN100 board. These diodes can be disconnected from the port by removing the R1 resistor array from its socket.

  • Page 52: Connectors

    C O N N E C T O R S The board provides many connectors for interfacing to an user hardware or standard devices like PC keyboard, RS232 communication line or CAN network. The connectors “Prototype connector”, “Simulated CPU ports”, “A/D connector”...
  • Page 53 K8-A/D connector This connector provides an access to the A/D port signals of the CPU: AVCC 1 2 AVCC AGND 3 4 AGND AVR+ 5 6 AVR+ ADTG 7 8 AVR- AN0 9 10 AN1 AN2 11 12 AN3 AN4 13 14 AN5 AN6 15 16 AN7...
  • Page 54 K2, K3-CAN connectors These connectors are of the “Canon 9 male” type. The pinout is following: Pin 2: CANL Pin 7: CANH Note: All the other pins are left unconnected. K5, K6, K7-RS232 interfaces These connectors are of the “Canon 9 female” type. The pinout is following: 1: NC 2: RX 3: TX...

  • Page 55: Switches

    K14-I C connector The type of this connector is “Header 4x1”. The pinout is following: 1: VCC 2: SDA 3: SCL 4: GND K12-FPGA JTAG port This connector allows testing of FPGA and its user-created configuration. User can use Xilinx standard cables for this purpose. K13-FPGA programming connector This connector allows reprogramming the FPGA with an user-created configuration.
  • Page 56 UMD2 UMD1 UMD0 Mode name Reset vector area External data bus witdth External vector mode 0 External External vector mode 1 External External vector mode 2 External Internal vector mode Internal (Mode data) Reserved Reserved Async serial programming Reserved *When FPGA detects this setting, it sets the logic levels on the CPU port P0 in the way that P00 and P01 pins of the CPU are pulled to ‘0’.

  • Page 57: Jumpers

    8:USW - The state of this switch (OR-ed with the state of UKEY), can be read in the SCDS register (address C0 ). Both Fujitsu debug monitor and PE debug kernel use this switch to find out whether to run the user program or not after reset.
  • Page 58 J7: UART0 RTS-CTS loopback When SHORT, this jumper makes the RTS-CTS loopback on the UART0 RS- 232 interface. UART1 RTS-CTS loopback When SHORT, this jumper makes the RTS-CTS loopback on the UART1 RS- 232 interface J21, J22, J23: UARTs to RS232 drivers connection jumpers These jumper headers are intended to provide access to the UART0, UART1 and User UART signals.
  • Page 59 J23 pinout: GND 1 2 GND SOTU 3 4 to RS232 input SINU 5 6 from RS232 output To User UART reset 8 from RS232 output for VCC 9 10 VCC RTSU 11 12 from RS232 output CTSU 13 14 from RS232 output NC 15 16 NC...
  • Page 60 Note: If the reset condition set by these jumpers is met, the D10 LED diode will shine and the CPU will be reset. User UART Serial line reset - polarity selection User UART serial line reset jumpers: In the 1-2 position, the “1” level on the DTR line will cause the CPU reset.
  • Page 61 J17: Speaker connection jumper If short, the amplifier output is connected to the built-in speaker. CAN interface J26: RX0 to INT4 connection jumpers: When short, the RX0 line of the CAN0 interface is connected to the INT4. This allows the programmer to use the “wake-up” mode of the CPU CAN interface. J27: RX1 to INT5 connection When short, the RX1 line of the CAN1 interface is connected to the INT5.
  • Page 62 J4: Programming mode(PRMODE) enable Miscellaneous jumpers: When REMOVED, the FPGA EEPROM works as an ordinary serial configuration PROM. When SHORT, the FPGA EEPROM is switched to the programming mode. In this mode it can be accessed as an I2C serial memory. The details about the EEPROM programming can be found in the FPGA EEPROM chapter.

  • Page 63: The Mainboard Programmer's Reference

    Chapter Chapter The Mainboard Programmer‘s Reference This section describes internal registers of the FPGA chip, which provides the biggest portion of the Mainboard functionality. The FPGA is connected to the CPU external bus, so it is necessary to program all the CPU external bus pins (including the CLK and /WRL pins) to the external bus mode with the 8-bit access to the 0C0H-0FFH area.

  • Page 64: Simulated Cpu Ports (P0, P1, P2, P3 Of Fujitsu Flash Cpu)

    S I M U L A T E D C P U P O R T S ( P 0 , P 1 , P 2 , F U J I T S U F L A S H C P U ) Registers Base Address: 000000 for CPU native ports, 0000D8...

  • Page 65: Add-On Fpga Ports

    DDR3 Initial Acces value Addr.: DF When reading the register, last value written to it is returned. Pins are controlled as described below: 0 = Input mode 1 = Output mode Note: Pull-up resistors 47K are internally connected to port pins. A D D - O N F P G A P O R T S...

  • Page 66: Add-On Fpga Output-Only Port

    A D D - O N F P G A O U T P U T - O N L Y P O R T On the remaining 6 FPGA User programmable pins there is an ouput only, 6bit port: (1) Port data register OPDR Initial...

  • Page 67: User Uart

    Output mode Read: The level at the corresponding pin is read. In most cases it will be the value written to the pin as last, the only exception can happen when the pin is erroneously pulled hard to VCC or GND. Write: Data is written to an output latch and output to the corresponding pin.
  • Page 68 Registers Base Address: 0000D0 (1) Data register SDAT Address: D0 Initial Value Note: R/W for I/O ports means the following: Read: The data from the receive buffer is read. Read clears the DR bit in the status register. Write: Data are written to the transmit buffer. (2) Line control register Address: D1 SBRK...
  • Page 69 [Bit 5] BI: Break Indicate bit is set when a Break Signal was received. It can be cleared by reading the LSR [Bit 4] FE: Framing error bit is set when stop bit is 0 during normal character (not a Break Signal) reception. Can be cleared by reading the LSR [Bit 3] OE: Overrun error bit is set when a new character is received but the...
  • Page 70 (1) Bus status register IBSR Address: C9 Read/Write (---) (---) (---) (---) (---) Initial Value (---) (---) (---) (---) (---) [Bit 7] BB: Bus Busy 0: The Stop condition was transmitted (initial value) 1: The Start condition was transmitted This bit should be polled when the MS bit of the IBCR register is changed by user.
  • Page 71 [Bit 4] MS: Master Transfer Start This bit controls I C data transfer. 0: The stop condition is generated and address data transfer terminated. 1: The start condition is generated and address data transfer started. [Bit 3] ACK: Acknowledge This bit enables acknowledge generation when data is received. •...

  • Page 72: Keyboard Controller

    =384 000/CS[3:0] The actual SCL clock frequency is dependent on the speed of devices that are connected to the I2C bus – see the “Clock synchronization” issue in the Philips’s I2C bus specification. (4) Data register IDAR Address: CC Read/Write (R/W) (R/W) (R/W)

  • Page 73: Led Display

    L E D D I S P L A Y Base Address: E8 (1) LED display data registers The double 7-segment LED display is controlled by two 8-bits wide, write-only registers LEDDR0 and LEDDR1. LEDDR0 [7:0] Address: E8 Read/Write Initial Value LEDDR1 [7:0] Address: E9...
  • Page 74 Mainboard reset button is pressed or power is removed and then applied again to the board while J4 is SHORT, the FPGA will not be configured so the Mainboard will not work properly. To return to the standard configuration mode, J4 must be removed. 2.

  • Page 75: System Control Registers

    S Y S T E M C O N T R O L R E G I S T E R S The system control registers allows to check and control Devkit16 configuration. (1) System control DIP switches status SCDS[7:0]...
  • Page 76 mirror function is analogic to CPU one and is similary default on after reset. When small model is selected, then FPGA decoding logic works as described on The Mainboard User Reference chapter for SMALL. RESET: when a ‘0’ to ‘1’ occurs on this bit, the CPU will be reset (a 100ms pulse will be generated on the #RST CPU pin).
  • Page 77 Memory maps for most frequently used modes: FFFFFFH Int. FLASH – FF bank FF0000H Int. FLASH – FF bank FFFFFFH FEFFFFH FF0000H Int. FLASH – FE bank FE0000H Int. FLASH – FE bank FEFFFFH FBFFFFH FE0000H Ext. FLASH 256K F80000H FPGA res.
  • Page 78 The address decoding and memory chip selects generation is done in the FPGA. Since the Devkit16 Mainboard can be delivered with external SRAM memories of 512K or 2M size, the FPGA decodes the address in a way that it reserves a 2M block in both the high memory block (HMB, 800000H-FFFFFFH) and lower memory block (LMB, 010000H-800000H).
  • Page 79 pins than the CPU would provide with all the external bus pins used. The memory map for the Adr/IO switch ON mode is shown on the following figure: FFFFFFH Not Available 100000H 00FFFFH Iimage of the area FF4000-FFFFFF 004000H Peripheral 003900H External 002000H...
  • Page 80 [Bit 0] MSEL – this bit holds the value of the MSEL jumper J10. When the jumper is short, this bit is ‘0’, otherwise it is ‘1’. When both the PE kernel and Fujitsu Softune monitor are present in the external FLASH memory,...
  • Page 81 PE kernel to decide whether to run the Fujitsu Softune Monitor or not. When MSEL=’0’, the Softune monitor will be run, otherwise (MSEL=’1’) the PE kernel remain active. [Bit 1] UKIE – when ‘1’, pressing the User Key button (or switching the User Key DIP switch ON) will produce a 25ms pulse on the INT0 CPU signal.
  • Page 82 1 2 3 4 5 6 7 8 Fig. 2:The Mainboard layout with default jumper setting (for Softune)

  • Page 83: Default Jumper Settings

    D E F A U L T J U M P E R S E T T I N G S These jumpers come in the SHORT position as a default factory setting: J1: The User UART serial line reset polarity is set for Softune. J5: The DTR line of UART1 serial interface is selected as a source for the serial line reset J9: The RTS-CTS hardware flow control is selected (not the loopback) J10: The Softune monitor is selected...

  • Page 84: What To Do If

    Chapter What to do if ... This chapter includes hints for DevKit16 operation, which should be checked before call technical support • The green LED on the Mainboard is blinking. What should I do ? 1. The MD0-MD2 CPU pins are pulled to '0' by some device.
  • Page 85 LED display, when you reset the mainboard). • The Fujitsu Softune debugger doesn’t start - the “Invalid communication status (or cable connection)” error message appears 1. Check the communication cable. It has to be connected properly on both sides.

  • Page 86: Get The Most From Devkit16

    Chapter Get the most from DevKit16 This chapter provides hints and tips how to benefit more from DevKit16 and its options. D O W N L O A D T H E C U R R E N T A N D...

  • Page 87: Devkit16 Power Supply Requirements

    S U P P L Y S U P E R V I S O R . Warning: If the DevKit16 is powered using the on-board stabilizer, the supply current must not exceed the 1A limit of the stabilizer. Before connecting any peripheral to the DevKit16, please check that its power supply current requirements doesn’t does not cause...

  • Page 88: Warranty And Disclaimer

    Product and any consequential damages in cases of unauthorised decompiling and/or reverse engineering and/or disassembling. Note, the DEVKIT16 and all its deliverables are intended and must only be used in an evaluation laboratory environment. Fujitsu Microelectronics Europe GmbH warrants that the Product...
  • Page 89 To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH disclaims all other warranties, whether expressed or implied, in particular, but not limited to, warranties of merchantability and fitness for a particular purpose for which the Product is not designated.

  • Page 90: Revision And Error List

    • Schematics bug on page 90 : J11 was connected to SDA instead of SCL and J12 to SCL instead of SDA. 15.02.2000 Points about burning Fujitsu debug monitor and PE V1.23 debug kernel added to the paragraph “Commonly used settings of the controls” (Chapter Flash It, page 27).
  • Page 91 Softune debug monitor are described there • In the chapter 6, the section “How to burn the CPU FLASH without Devkit16” was added • The chapter “What to do if” was updated • The pinout of the A/D connector on page 51 has 18.12.2000...

  • Page 92: Appendix

    Chapter Appendix Here you will find schematics of the CPU board for MB90F543, the Main board schematics, Interface bus and Device Bus description Device Bus (K2) and Interface Bus (K1 ) connectors pins: DIN Conn. Device Bus Interface Bus PIN NO. CPU Pin Nr.
  • Page 93 DIN Conn. Device Bus Interface Bus PIN NO. CPU Pin Nr. Function CPU PIN Nr. SIGNAL 2nd Function \HAK TIN0 TOT0 TIN1 SOT0 TOT1 SCK0 SIN0 SOT1 SCK1 SIN1 SOT2 SCK2 SIN2 OUT2/IN6 OUT3/IN7 PPG0 OUT0 PPG1 OUT1 TIN1 OUT3/IN7 ADTG OUT2/IN6 TOT1...
  • Page 94 DIN Conn. Device Bus Interface Bus PIN NO. CPU Pin Nr. Function CPU PIN Nr. SIGNAL 2nd Function OUT2/IN6 OUT3/IN7 NC(SGO) NC(SGA) X1AJ X0AJ...
  • Page 95 SERRES HEADER 6 #HST RSTX R13 10K AD00 22pF 32.768KHz MB90540 100N 100N 10M/25V R14 10K AD01 LED 5mm Title Devkit16 - CPU Board 22pF SW DIP-8 Size Number Revision Ver. 1 Date: 18-Dec-2000 Sheet of File: D:\Designs\Unis\Pcb\cpuboard13\Cpuboard13.ddb Drawn By:...
  • Page 96 AD00 SPEED SP20 SP21 BusCtrl[0..7] BusCtrl[0..7] BYTE BYTE SUSPND RY/BY RY/BY HEADER 13X2 Simulated ports 0-3 #USBOE Addr_IO Addr_IO SPEED HEADER 4 HEADER 8 Title DevKit16 Mainboard Size Number Revision Ver. 1 Date: 11-Nov-1999 Sheet of File: D:\Devkit16v13.Ddb Drawn By:...
  • Page 97 CAN 9 Z 90 T1IN T1OUT T2IN T2OUT SOT0D LED 3mm Red SIN0D R1OUT R1IN #RESP0 R2OUT R2IN 100n HEADER 5X2 JUMPER3 MAX232A #RESP1 Title DevKit16 Mainboard - Serial IF Size Number Revision Ver. 1 Date: 10-Feb-2000 Sheet of File: D:\Devkit16v13.Ddb Drawn By:...
  • Page 98 SP00 AD11 IO84 IO201 CSLED0 AD10 SP[0..37] IO85 IO204 CSLED1 IO87 IO205 AD[0..15] CSU1 IO88 IO206 CSU2 IO89 CSLED[0..1] CSU[0..2] XCS20-4 TQ(208)C Title DevKit16 Mainboard - FPGA Size Number Revision Ver. 1 Date: 3-Feb-2000 Sheet of File: D:\Devkit16v13.Ddb Drawn By:...
  • Page 99 SDAU Serial EEPROM SCLU JUMPER3 JUMPER3 SCLU SDAU IC10 SCLB SDAB SCLB SDAB JUMPER2 24C08B-E/SN HEADER 4 I2C Header Title DevKit16 Mainboard - LED Disp. and EEPROM Size Number Revision Ver. 1 Date: 11-Nov-1999 Sheet of File: D:\Devkit16v13.Ddb Drawn By:...
  • Page 100 A18M AD14 BYTE AD15 #BYTE #WRL RY/BY RY/#BY #RST SN74HCT573M #RESET MBM29F200BA-70PF AD[0..15] A[16..23] AD[0..15] CSRAM[0..1] A[16..23] CSFLASH BusCtrl[0..7] BYTE Title DevKit16 Mainboard - Memories Addr_IO AD15/A00 Size Number Revision Ver. 1 Date: 11-Nov-1999 Sheet of File: D:\Devkit16v13.Ddb Drawn By:...
  • Page 101 CAN 9 V 90 JUMPER2 74HCT32 IC11 CANH INT5 JUMPER2 Vref HEADER 5X2 CANL PCA 82C250T CAN 9 V 90 Title DevKit16 Mainboard - CAN and sound IF Size Number Revision Ver. 1 Date: 17-Jan-2000 Sheet of File: D:\Devkit16v13.Ddb Drawn By:...

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