Board Level Mounting; Rework - Xilinx Virtex-4 QV FPGA Manual

Chapter 6: Guidelines for Xilinx CF Package Handling and Assembly
Any inspection of parts should be made while keeping the part in its shipping tray because
the columns might be damaged if the part is manually handled or removed from the tray.
Careful handling of the parts during board mount is recommended to ensure no damage to
the chip capacitors occurs. Xilinx performs a 50–100X magnification of the chip capacitors
before shipment and rejects any part that shows chip outs on the capacitors that occur on
the chip capacitor terminals or any cracks in the chip capacitors.

Board Level Mounting

Xilinx recommends the customer perform a visual inspection at different steps of the
process to ensure that no damage has been induced to the package, columns, or
decoupling chip capacitors (at 50X magnification) due to mishandling issues.
Note:
and with total assembly requirements as driven by other components on the product.
Xilinx recommends PCB design rules for each of our packages. These rules are specified in
UG112, Device Package User Guide.
For additional CGA board mounting information, refer to the IBM CBGA Surface Mount
Assembly and Rework User Guide at
https://www-
01.ibm.com/chips/techlib/techlib.nsf/techdocs/BBA0EE9ED5C3DC8B87256F1800732B9
4/$file/cbga_assy_rework.pdf
Xilinx recommends that the reflow profile recommended by the solder paste supplier be
used. For the cleaning process, Xilinx recommends caustic solvents not be used during the
cleaning cycle. Xilinx recommends DI water rinse and bake are used.
The recommended maximum reflow temperature is 220°C. However, a maximum peak
temperature of 235°C can be acceptable. (Refer to page 87 of IBM CBGA Surface Mount
Assembly and Rework User Guide.)
For solder joint test method (X-rays, X-ray CT, fiberscope, and so on) of inline or failure
detection in evaluation test (crack, void, alignment, and so on), IBM® has identified
transmission X-ray to detect solder bridging and X-ray laminography to detect solder joint
opens. (Refer to page 24 of IBM CBGA Surface Mount Assembly and Rework User Guide.)
Most of the heat is dissipated from the columns. Xilinx has measured thermal resistance
numbers for these packages.

Rework

Xilinx does not recommend any rework or staking of the CF packages.
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The design and process requirements should be compatible with standard SMT equipment
www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging
UG496 (v1.1) June 8, 2012
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