Table of Contents
Advertisement
Chapter 1: XM104
Board Technical Description
The XM104 provides a number of connectors which break out the FPGA multi-gigabit
transceiver (MGT) interface signals to and from the board interface.
block diagram of the XM104. Each MGT data port interface consists of two differential
pairs of MGT signals, one pair for the transmitter and one pair for the receiver. MGT Data
Ports 0 and 1 are each wired to four SMA connectors. MGT Data Ports 2 and 3 are each
wired to host Serial ATA connectors J11 and J12 respectively. MGT Data Ports 4 through 7
are wired to a 10GE Base-CX4 connector supporting a XAUI application interface. MGT
transmitter Data Ports 8 and 9 are electrically looped back to the board receiver ports 8 and
9 respectively. The ML605 does not support Data Port 8 and 9 interfaces.
Silicon Laboratories Si570 serial IIC bus reprogrammable LVDS clock source and a Si5368
any-rate precision clock multiplier and jitter attenuator integrated circuits provide a
variety of programmable differential clock sources to the board's FGPA. The Si5368
integrated circuit receives three differential LVDS clock inputs from the board and outputs
five LVDS differential clock outputs to the FPGA.
A 2 Kb serial IIC EEPROM is also connected to the IIC interface of the board providing
non-volatile storage. The serial IIC interface also connects to the Si570 and Si5368
integrated circuits enabling the board's FPGA to program the clock circuitry on the XM104.
X-Ref Target - Figure 1-2
10
J1 FMC HPC Interface
MGT Data Port 0
DP0
SMA (4x)
J3, J4, J5, J6
MGT Data Port 1
DP1
SMA (4x)
J7, J8, J9, J10
MGT Data Port 2
DP2
Serial ATA J11
MGT Data Port 3
DP3
Serial ATA J12
MGT Data Ports 4-7
DP4-DP7
10GE Base-CX4 J2
MGT Data Ports 8-9
DP8-DP9
Electrical Loopback
Figure 1-2: XM104 Block Diagram
www.xilinx.com
GBTCLK0_M2C
CLK0_M2C
CLK1_M2C
CLK2_M2C
CLK3_M2C
Level
Shifter
LA00_CC
LA01_CC
LA17_CC
IIC
Switch
IIC
GBTCLK1_M2C
FMC XM104 Connectivity Card User Guide
UG536 (v1.1) September 24, 2010
Figure 1-2
shows a
Si5368
CKOUT1
FS_OUT
CKOUT2
CKOUT3
CKOUT4
Any-rate Clock
CKIN1
CKIN3
CKIN4
CKIN2
Si570
Clock
Clock
156.25 MHz
Driver
2 K b
EEPROM
UG536_02_120309
Advertisement
Table of Contents
