Adc Interface - YUGE CLM920 TD3 Usage Manual

CLM920 TD3 LTE Module Hardware Usage Guide
Figure 3-26 Schematic diagram of the Ethernet application solution
CLM920 TD3 module SGMII interface and Ethernet PHY chip AR8033 reference design
as shown below:
Figure 3-27 SGMII interface and Ethernet PHY core AR8033 reference design

3.18 ADC interface

The CLM920 TD3 provides two analog-to-digital converter interfaces to read the voltage
value. The input voltage of the ADC interface cannot exceed VBAT. It is recommended that
the ADC pin be input with a voltage divider circuit.
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Table 3-27 ADC Pin Definitions
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