Boot Timing - YUGE CLM920 TD3 Usage Manual

CLM920 TD3 LTE Module Hardware Usage Guide

3.4.2 Boot timing

Symbol Description
Ton Boot low level width
Ton(status) Boot time (according to status status)
Ton(usb) Boot time (according to usb status)
Ton(uart) Boot time (according to uart status)
VIH PWRKEY input high level
VIL PWRKEY input low level
It is recommended to use the open-collector drive circuit to control the PWRKEY, which
can be released after pulling the base level for 500ms. At this point, the module is powered on.
Switching machine design can also be done with buttons, button accessories need to be placed
with a TVS tube for ESD protection.
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Figure 3-7 Startup timing diagram
Table 3-6 Boot timing parameters
Min Typical
100 500
22 -
- 10
- 6
0.6 0.8
-0.3 0
Max unit
- ms
- ms
- s
- s
1.8 V
0.5 V
- 32 -