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CLM920 TD3 LTE Module Hardware Usage Guide
40
I2S_CLK
The following figure shows the reference design of the CLM920 TD3 connected to the
NAU8810:
3.15 MCLK interface
The CLM920 TD3 module provides one MCLK and provides a 12.288M clock output.
This interface is mainly used to connect the MCLK of the CODEC chip. The main clock
frequency of the NAU8810 is supported by default.
Signal
Pin
I/O
name
116
MCLK
D0
Shanghai Yuge Information Technology co., LTD
IO
I2S clock
Figure 3-24 I2S to analog voice map
Table 3-24 MCLK Pin Definitions
Param
Description
eter
VOH
I2S master
clock
VOL
VOH
1.35
1.8
VOL
0
VIH
1.2
1.8
VIL
-0.3
Level value (V)
Min
Typical
Max
1.35
1.8
2
0
0.45
2
0.45
2
0.6
Remarks
The default output
is 12.288M
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