Sgmii Interface - YUGE CLM920 TD3 Usage Manual

CLM920 TD3 LTE Module Hardware Usage Guide
Figure 3-25 Wireless connection interface and YG30 reference design
The SDIO interface supports single rate mode with a maximum frequency of 50MHz.
The SDIO interface has a high rate. To ensure that the interface design conforms to the SDIO
3.0 specification, the following guidelines are recommended:
 The SDIO signal line requires a three-dimensional package and the impedance needs
to be controlled at 50Ω ± 10%.
 SDIO signal lines need to be away from sensitive signals such as RF, analog signals,
and noise signals such as clocks and DCDCs.
 The SDC1_CLK signal line needs to be placed close to the module to place 15Ω~24
Ω termination matching resistor; the SDC1_CLK pin to resistor should be less than 5mm.
 The spacing between the SDIO signal and other signals needs to be greater than 2
line widths and ensure that the bus load is less than 15pF.
 SDC1_CLK and SDC1_DATA[0:3]/SDC1_CMD need to be treated as equal length
(with a difference of less than 1mm), and the total length should be less than 50mm.

3.17 SGMII interface

The CLM920 TD3 module provides an SGMII interface with embedded Ethernet MAC
and a two-wire management interface. The key features are as follows:
 Comply with the IEEE 802.3 standard.
 Support 10/100/1000M working mode.
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