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CLM920 TD3 LTE Module Hardware Usage Guide
SDC2_
31
IO
D0
SDC2_
32
DO
CLK
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VIH
VIL
VOH
VOL
VIH
VIL
VOH
VOL
VIH
VIL
SDIO bus
DATA0
VOH
VOL
VIH
VIL
VOH
SDIO
Bus clock
VOL
1.27
1.8
-0.3
0.75*
2.95
VDD_Px
0
0.625*
2.95
VDD_Px
-0.3
1.35
1.8
0
1.27
1.8
-0.3
0.75*
2.95
VDD_Px
0
0.625*
2.95
VDD_Px
-0.3
1.35
1.8
0
domain
2
1.8V voltage
domain
0.6
1.8V voltage
domain
VDD_Px 2.95V voltage
domain
0.125*
2.95V voltage
VDD_Px
domain
VDD_Px
2.95V voltage
+ 0.3
domain
0.25*
2.95V voltage
VDD_Px
domain
2
1.8V voltage
domain
0.45
1.8V voltage
domain
2
1.8V voltage
domain
0.6
1.8V voltage
domain
VDD_Px 1.8V voltage
domain
0.125*
2.95V voltage
VDD_Px
domain
VDD_Px
2.95V voltage
+ 0.3
domain
0.25*
2.95V voltage
VDD_Px
domain
2
1.8V voltage
domain
0.45
1.8V voltage
domain
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