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CLM920 TD3 LTE Module Hardware Usage Guide
The maximum downlink rate is 150Mbs and the maximum uplink rate is 50Mbs (in
4G network).
Support for VLAN tagging.
Supports 3EEE 1588 and PTP protocols.
Can be connected to an external Ethernet PHY chip such as the AR8033, or an
external switch.
Management interface supports 1.8V/2.85V dual voltage.
The SGMII interface pin is defined as follows：
Pin
Signal name
119
EPHY_RST_N
120
EPH_INT_N
121
SGMII_MDATA
122
SGMII_MCLK
128
USIM2_VDD
123
SGMII_TX_M
124
SGMII_TX_P
125
SGMII_RX_P
126
SGMII_RX_M
Ethernet application plan:
Shanghai Yuge Information Technology co., LTD
Table 3-26 SGMII interface pin definition
Description
Ethernet PHY reset
Ethernet PHY interrupt
SGMII MDIO data
SGMII MDIO clock
SGMII_MDATA pull-up
power supply
SGMII differential data
transmission negative signal
SGMII differential data
transmission positive signal
SGMII differential data
receiving positive signal
SGMII differential data
receiving negative signal
IO
Remarks
DO
1.8V/2.85 voltage
domain
DI
1.8 voltage domain
IO
1.8V/2.85 voltage
domain
DO
1.8V/2.85 voltage
domain
PO
1.8V/2.85 voltage
domain
0.1μF capacitor in
AO
series near the chip end
Connect 0.1μF
AO
capacitor in series near
the chip end
Connect 0.1μF
AI
capacitor in series near
the module end
Connect 0.1μF
AI
capacitor in series near
the module end
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