AOpen AX5TC User Manual page 63

AWARD BIOS
Chipset Features à DRAM Page Idle Timer
DRAM Page Idle
This item determines the amount of time in CPU
Timer clocks that DRAM page will be close after CPU
becomes idle.
2 Clks
4 Clks
6 Clks
8 Clks
Chipset Features à DRAM Enhance Paging
DRAM Enhance When Enabled, TX chipset will keep DRAM page
Paging
open as long as possible according to enhanced
method.
Enabled
Disabled
Chipset Features à SDRAM(CAS Lat/RAS-to-CAS)
SDRAM(CAS
These are timing of SDRAM CAS Latency and RAS
Lat/RAS-to-CAS) to CAS Delay, calculated by clocks. They are
important parameters affects SDRAM performance,
2/2
default is 2 clocks. If your SDRAM has unstable
3/3
problem, change 2/2 to 3/3.
Chipset Features à SDRAM Speculative Read
SDRAM Speculative
Enable this item reduce one clock of SDRAM read
Read leadoff timing by presenting the SDRAM read request
before the controller chip decodes the final memory
Enabled
target. This Item must be Disabled if more than one
Disabled
DIMM is installed in the system.
Chipset Features à System BIOS Cacheable
System BIOS
Enabling this item allows you to cache the system
Cacheable BIOS to further enhance system performance.
Enabled
Disabled
3-14