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Chipset Features à DRAM Read Burst (EDO/FP)
DRAM Read Burst
(EDO/FP)
x444/x444
x333/x444
x222/x333
Chipset Features à DRAM Write Burst Timing
DRAM Write Burst
Timing
x444
x333
x222
Chipset Features à Fast EDO Lead Off
Fast EDO Lead Off
Enabled
Disabled
Chipset Features à Refresh RAS# Assertion
Refresh RAS#
Assertion
5 Clks
4 Clks
Read Burst means to read four continuous memory
cycles on four predefined addresses from the DRAM.
The default value is x222/x333 for 60ns EDO or FPM
(Fast Page Mode) DRAM. Which means the 2nd,3rd
and 4th memory cycles are 2 CPU clocks for EDO
and 3 clocks for FPM. The value of x is the timing of
first memory cycle and depends on the "DRAM
Leadoff Timing" setting.
Write Burst means to write four continuous memory
cycles on four predefined addresses to the DRAM.
This item sets the DRAM write timing of the 2nd,3rd
and 4th memory cycles. There is no difference of
EDO and FPM DRAM on the write burst timing. The
value of x depends on the "DRAM Leadoff Timing"
setting.
This item enables fast EDO read timing, results 1
clock pull-in for read leadoff latency of EDO read
cycles. It must be Disabled, if any FPM DRAM is
installed.
This item controls the number of clocks RAS is
asserted for refresh cycle.
AWARD BIOS
3-13
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