Kenwood NX-200 Service Manual page 36

NX-200
5. PLL Frequency Synthesizer
5-1. VCTCXO (X1)
VCTCXO (X1) generates a reference frequency of
19.2MHz for the PLL frequency synthesizer. This reference
frequency is applied to pin 9 of the PLL IC (IC3) and is con-
nected to the IF circuit as a 2nd local signal through the
Tripler (Q201). The VCTCXO oscillation frequency is deter-
mined by the DC voltage of the VC terminal. The VC voltage
is fi xed to 1.65V by R59 and R60, and supplied to the VC
terminal through IC5. The modulation signal is also fed to
VC terminal through IC5.
The frequency adjustment is achieved by switching the
ratio of dividing frequency that is not adjusted by the DC
voltage impressed to VC. The resolution of the adjusting fre-
quency is approximately 8Hz. Because twice the VCO out-
put are input for the input frequency of PLL IC, the sending
and receiving frequency can be adjusted by approximately
4Hz resolution.
5-2. VCO
There is a RX VCO and a TX VCO.
The TX VCO (Q10) generates a transmit carrier and the
RX VCO (Q8) generates a 1st local signal. For the VCO oscil-
lation frequency, the transmit carrier is 136 to 174 MHz and
the 1st local receive signal is 194.05 to 232.05MHz.
The VCO oscillation frequency is determined by one sys-
tem of operation switching terminal "T/R" and two systems
of voltage control terminals "CV" and "ASSIST".
The operation switching terminal, "T/R", is controlled by
the control line (/T_R) output from the ASIC (IC108). When
the /T_R logic is low, the VCO outputs the transmit carrier
and when it is high, it outputs a 1st local receive signal.
The voltage control terminals, "CV" and "ASSIST", are
controlled by the PLL IC (IC3) and ASIC (IC108) and the
output frequency changes continuously according to the
applied voltage. For the modulation input terminal, "VCO_
MOD", the output frequency changes according to the
applied voltage. This is used to modulate the VCO output.
"VCO_MOD" works only when "/T_R" is low.
5-3. PLL IC (IC3)
The PLL IC compares the differences in phases of the
VCO oscillation frequency and the VCTCXO reference
frequency, returns the difference to the VCO CV terminal
and realizes the "Phase Locked Loop" for the return con-
trol. This allows the VCO oscillation frequency to accurately
match (lock) the desired frequency.
When the frequency is controlled by the PLL, the fre-
quency convergence time increases as the frequency differ-
ence increases when the set frequency is changed. To sup-
plement this, the ASIC is used before control by the PLL IC
to bring the VCO oscillation frequency close to the desired
frequency. As a result, the VCO CV voltage does not change
and is always stable at approximately 2.5V.
The desired frequency is set for the PLL IC by the ASIC
(IC108) through the 3-line "SDO1", "SCK1", "/PCS_RF"
serial bus. Whether the PLL IC is locked or not is monitored
by the ASIC through the "PLD" signal line. If the VCO is not
the desired frequency (unlock), the "PLD" logic is low.
36
CIRCUIT DESCRIPTION /
电路说明
5. PLL 频率合成器
5-1. VCTCXO(X1)
VCTCXO(X1) 为 PLL 频率合成器产生 19.2MHz 的基准频率。
该基准频率被施加到 PLL IC(IC3) 的第 9 针，作为第 2 本振
信号通过三倍频器 (Q201) 后送到 IF 电路。VCTCXO 振荡频率
由 VC 端子的 DC 电压决定。 VC 电压由 R59 和 R60 固定为 1.65V，
通过 IC5 施加于 VC 端子。调制信号也通过 IC5 送入 VC 端子。
通过切换未经外加到 V C 的 D C 电压调整的分割频率的比率，
实现频率调整。调整频率的分辨率约为 8Hz。由于 PLL IC 的
输入频率输入两倍的 V C O 输出，发送频率和接收频率可按照
约 4Hz 的分辨率进行调整。
5-2. VCO
有一个 RX VCO 和一个 TX VCO。TX VCO(Q10) 生成发射载波，
RX VCO(Q8) 生成第 1 本振信号。对于 VCO 震荡频率，发射载
波为 136 到 174M H z，第 1 本振信号为 194.05 到 232.05M H z。
V C O 震荡频率由一个操作切换端子"T / R"系统和两个电压控
制端子"CV"和"ASSIST"系统决定。操作切换端子"T/R"
由 ASIC(IC108) 输出的控制线路 (/T_R) 进行控制。/T_R 逻辑
较低时，VCO 输出发射载波，较高时，输出第 1 本地接收信号。
电 压 控 制 端 子"C V" 和"A S S I S T" 由 P L L I C ( I C3 和
A S I C ( I C108) 控制，输出频率根据施加的电压持续改变。对
于调制输入端子"VCO_MOD" ，输出频率根据施加的电压改变。
籍此调制 VCO 输出。 "VCO_MOD"仅在 "/T_R"低时工作。
5-3. PLL IC(IC3)
P L L I C 对比 V C O 震荡频率和 V C T C X O 基准频率的相位差，
将相位差返回 VCO CV 端子，实现返回控制的"锁相环路" 。
这可以使 VCO 震荡频率与所需的频率精确匹配 ( 锁定 )。
频率由 P L L 控制时，频率锁定时间将随着设定频率改变时
频率差的增大而增加。为对此进行补充，在由 PLL IC 控制之
前使用 A S I C 以使 V C O 震荡频率接近所需的频率。因此，V C O
CV 的电压不变，始终稳定在约 2.5V。
P L L I C 的所需电压由 A S I C ( I C108) 通过 3 线路"S D O1" ，
"SCK1" ， "/PCS_RF"串行总线进行设置。PLL IC 是否锁定由
ASIC 通过"PLD"信号线路进行监测。如果 VCO 不是所需的频
率 ( 失锁 )，则"PLD"逻辑较低。