Sony PCS-1500 Service Manual page 113

3-2. Circuit Description of the Respective Boards
[VCP block]
The VCP block consists of VCPex (IC300), the two 4-Mbit SRAMs (IC301, IC302) that are used for
storing program code and as the work area RAM, and the four 16 Mbit-DRAMs (IC303 to IC306) that are
used as the picture data buffer.
The VCP block has the following functions: separating the video data, audio data and other data from the
received line data; multiplexing the transmitting video and audio data into the transmission data that is
sent to the line; compression and decompression of the video signal; generation of the P-in-P display; and
generation of the split display when multiple points are connected. The program code that is required to
operate the VCPex (IC300) is downloaded from the CPU and saved in the SRAMs (IC301, IC302).
Downloading is performed by the software of the CPU and that of VCPex.
Fig. 3-13 shows connection with VCPex (IC300) and the system bus, connection with the AC block,
connection with the NETIF block, and connection with the SRAMs (IC301, IC302) and DRAMs (IC303
to IC306). The operating clock (40 MHz) is supplied from the crystal oscillator (X300). Among the
connection with the system bus, the READ/WRITE pulse uses the "HRD_VCP" and "HWR_VCP"
signals that are exclusive to VCPex (IC300). The interrupt signal "IRQ_VCP" is also output here.
The line data is transmitted to and received from the TDM_ASIC (IC750) of the NETIF block in the form
of a serial signal. The clock and frame sync signals are supplied from the TDM_ASIC (IC750).
Audio data is transmitted to and received from the Audio Code ICs (IC520, IC530) of the AC block. The
clock and frame sync signals are supplied from the Serial Timing Generator (IC501). However, the
trigger signal that generates the frame sync signal is output from the "AUX6, AUX7" output of the
VCPex (IC300).
The input video data is supplied from the VIDAD block. The output video data is sent to the VIDDA
block. Fig. 3-14 shows the video input/output signal interface of VCPex (IC300).
The fundamental clock signal of video data input/output is the 27 MHz clock that is supplied from the
Graphic Overlay ASIC (IC352). (The clock signal is buffered by IC354 that is not shown in Fig. 3-14.)
The input video data is the pixel data consisting of the 8-bit luminance signal and the 8-bit chrominance
signals that are supplied from the Pre-filter ASIC (IC350). The 13.5 MHz pixel clock is also output from
the Pre-filter ASIC (IC350). As the V sync and the field ID signal, the buffered signals that are output
signals of the Video Decoder (IC400) are used. (Software is set the V sync signal to be active low.) The
H sync signal that is ORed signal of "HSYNC (that is set to active-high)" and "DVALID (that is set to
active-low)" of the Video Decoder (IC400), is generated from the logic-OR gate (IC355).
The output video data is pixel data consisting of the 8-bit luminance signal and the 8-bit chrominance
signals, and the blanking signal that are output to the Graphic Overlay ASIC (IC352). The 13.5 MHz
pixel clock, H sync signal, V sync signal and field ID signals are output from the Graphic Overlay ASIC
(IC352).
Among the general-purpose ports "AUX0 to AUX7" of VCPex (IC300), "AUX0 to AUX3" are used to
set the Pre-filter ASIC (IC350). "AUX4" is used as the input port of the field ID signal for the output
video data. "AUX6 and AUX7" are used as the trigger output that generates the frame sync signal in the
serial signal for the AC block.
The VCP block is reset by the "RES_VCP" signal that is supplied from the CPU block.
It operates on the +3.3 V-2 power supply voltage.
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PCS-1500/1500P