Sony PCS-1500 Service Manual page 112

3-2. Circuit Description of the Respective Boards
HA1-5
5
\HRD,\HWR
2
\RES_OP,\
HCS_OP
2
\DEN_OP
HD0-7
8
HD8-15
8
\HCS_TDM
IRQ_TDM
\RES_ALL
from/to
CPU BLOCK
SIRCSIN_SEL
to SIRCS BLOCK
SIRCS_IF
SP_MUTE
to AUANA BLOCK
(IC604)
OUT_MUTE
to IC704,
\STBLED_ON
PWR BLOCK
\DOWNLOAD
to BRI BLOCK
MODE_SET
Vcc=3.3V-2
Buffer(IC703)
to AC BLOCK(IC500)
LV_NET8K
from/to
VCP BLOCK
VCP_TDMFS
VCP_TDMCK
VCP_TDMDR
VCP_TDMDX
3-22
to CPU BLOCK
\IRQ_LAN
\WAIT_OP
TDM ASIC(IC750)
uPD65646GJ-171
\HCS CK8K3
HA CK64K3
3-0
4
\HRD RBA3
\HWE RBB3
HD TBA3
7-0
8
TBB3
HINT
CK8K2
\RESET CK64K2
RBA2
RBB2
TBA2
PE7 TBB2
PA0-7,PB,
PC0-7,PD,PF
19
CK8K1
PE5 CK64K1
PE4 RBA1
RBB1
PE3 TBA1
TBB1
PE1
PE0 NETINTB
CLK12M
ST2
RT2
RD2
NETW8K SD2
TDMFS ST1
TDMCK RT1
TDMDR RD1
TDMDX SD1
Fig. 3-12 NETIF Block
Buffer(IC754,758)
A1-5
5
\RD,\WR
2
\RESET,\CS
2
\DEN
Transceiver(IC755)
D0-7
8
8
\OE1
\OE2
DIR
Buffer(IC756)
from/to CN750
(Optional Board)
\G
Buffer(IC751,752)
CK8K_BRI3
CK64K_BRI3
RBA_BRI3/D9
RBB_BRI3/D8
TBA_BRI3/D11
TBB_BRI3/D10
CK8K_BRI2
CK64K_BRI2
RBA_BRI2/D13
RBB_BRI2/D12
TBA_BRI2/D15
TBB_BRI2/D14
\G
CK8K_BRI1
CK64K_BRI1
RBA_BRI1
from/to
BRI BLOCK
RBB_BRI1
TBA_BRI1
TBB_BRI1
\NETOPINT
Buffer(IC752)
\G
\INT_BRI from BRI BLOCK
Buffer(IC753)
12.288MHz
CK12M to BRI BLOCK
Buffer(IC753)
ST_V.35
RT_V.35
RD_V.35
Buffer(IC753)
SD_V.35
\G
Buffer(IC752)
\G
\LAN_EN
PCS-1500/1500P