Intel 82801EB Programmer's Reference Manual page 57

R
}
Else
{
}
}
Device( DRV0) // Logical secondary master (SATA Port 0/1, or P-ATA device 0)
{
Name( _ADR, 0)
//
// similar to current P-ATA implementations. Since this
// device node can represent either a P-ATA device or a SATA
// device, a check may need to be added since the task file
// could be different.
SATA Programmer's Reference Manual
// enabled state as they (the device drivers) may have
// been designed for P-ATA and 'know' nothing about the
// PCS register
//
// Since Enhance mode implements a master-master scheme,
// only 1 port would be disabled here (dependent on the
// MAP settings). In Combined mode, both SATA ports are
// viewed as a single logical channel implementing a
// master-slave configuration in which case both ports
// are disabled.
//
If( LEqual( Local0, 2))
{
Store( 0x0, PCS)
}
If( LEqual( Local0, 5)
{
NAnd( PCS, 0x01, PCS) // only disable port 0
}
If( LEqual( Local0, 6)
{
NAnd( PCS, 0x02, PCS) // only disable port 1
}
// Disable Power to the device - Set the GPIO bit
// corresponding to the power plane control, platform
// specific
//
... // platform specific
// Is Combined mode and is a P-ATA device
....
// is combined, disable both ports
Theory of Operation
57