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R
A.5
ACPI Control Method (GSPS)
//
// Define where the SATA MAP and Status/Control registers reside in PCI Config
// space
//
OperationRegion(IDEC,PCI_Config,0x90,3)
Field(IDEC,ByteAcc,NoLock,Preserve)
{
MAP, 8, // SATA Map register - Offset 90h
, 8, // skip 8 bits
PCS, 8 // SATA Port status and control register - Offset 92h
}
Device( IDE1) {
Name(_ADR, 0x01f0002)
Device( PRID) { // Primary channel
Name( _ADR, 0)
// Assumes BIOS populated the SATA timing registers appropriately
// depending on which port is configured as primary and secondary
//
// This control method determines if device(s) are present on the logical
// primary channel.
// devices and because P-ATA does not
// have equivalent registers, this control will indicate a status of
// unknown (P-ATA only)
//
// Entry:
//
// Exit:
//
//
//
//
//
//
Method( GSPS, 0) // Get the port status for the device(s)
{
SATA Programmer's Reference Manual
// SATA controller
// Device 31, Function 2
// Logical primary channel (Port 0 or 1, BIOS selectable).
Because this control method is shared with P-ATA
Nothing
DWORD value representing the channel status:
0 ==> no devices present
1 ==> master device present
2 ==> slave device present
-1 ==> Not supported or unknown (P-ATA)
// need to figure out which port(s) to look at (e.g. are we in a
// master-master configuration or master-slave)
//
Store( Zero, Local0)
Theory of Operation
43
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