Intel 82801EB Programmer's Reference Manual page 36

Theory of Operation
}
}
Device( SECD) { // Secondary channel
Name( _ADR, 1)
Device( DRV0) // Logical secondary master
{
}
//
// Handle transitions to D0 power state
//
Method(_PS0,0)
{
36
// we need to disable the SATA ports here
//
// Since enhance mode implements a master-master scheme, only 1 port
// would be disabled here (dependent on the MAP settings). In Combined
// mode, both SATA ports are viewed as a single logical channel
// implementing a master-slave configuration in which case both ports are
// disabled.
//
Store( Zero, PCS) // disable ports 0 and 1 – assume combined mode
//
// Disable Power to the device - Set the GPIO bit corresponding to the
// power plane control
//
... // platform specific
// Logical secondary channel (Port 0 or 1, BIOS selectable)
Name(_ADR, 0)
...
//
// make sure the OS drivers finds the ports in an enabled state as they
// (the device drivers) may have been designed for P-ATA and 'know'
// nothing about the PCS register
//
// Since enhance mode implements a master-master scheme, only 1 port
// would be enabled here (dependent on the MAP settings). In Combined
// mode, both SATA ports are viewed as a single logical channel
// implementing a master-slave configuration in which case both ports
// are enabled.
//
//
// Enable Power to the device - Set the GPIO(s) bit corresponding to the
// power plane control. This shall be done before
// the port(s) are enabled. This is platform specific
SATA Programmer's Reference Manual
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