Map Register Programming; Pcs - Port Control And Status Register - Offset 92H - Intel 82801EB Programmer's Reference Manual

Serial ata controller
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R
4.2.2

MAP Register Programming

As shown in Figure 8. Enhanced Configuration, enhanced mode configures the SATA so each
SATA port is viewed as individual logical channels with a single master device. Using the MAP
register, the logical SATA channels can be configured so that port 0 is the logical primary channel
and port 1 is the logical secondary channel or vice-versa. The programming for this register is as
follows:
• MAP.MV == '000b'. This indicates that a SATA device on port 0 behaves as a master device
on the logical primary channel and a device on port 1 behaves as a master device on the
logical secondary channel.
• MAP.MV == '001b'. This indicates that a SATA device on port 0 behaves as a master device
on the logical secondary channel and a device on port 1 behaves as a master device on the
logical primary channel.
When in Enhanced mode, programming the MAP register to values other than '000b' or '001b'
could result in undefined hardware behavior. The MAP register shall be programmed by the BIOS
only during POST.
4.3
PCS - Port Control and Status Register – Offset 92h
To provide better power management and device presence capabilities, the SATA host controller
implements a Port Control and Status (PCS) register. The PCS register provides improved
power savings in that it allows system software to disable individual SATA ports. Device presence
detection is beneficial to system software as this can greatly reduce boot times and resume times
(from S3 and below).
Bit
7:6
5
4
3:2
1
0
SATA Programmer's Reference Manual
Type
Reset
RO
0
Reserved
Port 1 Present (P1P): When set, the SATA host has detected the presence
RO
0
of a device on port 1. It may change at any time. This bit is cleared when the
port is disabled via the P1E bit (bit 1 of this register).
Port 0 Present (P0P): When set, the SATA host has detected the presence
RO
0
of a device on port 0. It may change at any time. This bit is cleared when the
port is disabled via the P0E bit (bit 0 of this register).
RO
0
Reserved
Port 1 Enabled (P1E): When set, the port is enabled. When cleared, the port
is disabled. When enabled, the port is in the "on" state and can detect
devices. When disabled, the port is in the "off" state and cannot detect any
RW
0
devices.
Port 0 Enabled (P0E): When set, the port is enabled. When cleared, the port
is disabled. When enabled, the port is in the "on" state and can detect
devices. When disabled, the port is in the "off" state and cannot detect any
RW
0
devices.
Theory of Operation
Description
23

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