Additional Register Support; Map - Address Map Register - Offset 90H - Intel 82801EB Programmer's Reference Manual

Theory of Operation
4.1.1

Additional Register Support

Support of certain Compatible configuration options requires that the ICH5 implement an
additional hardware register that is configurable via BIOS. This register is located in the SATA
function's PCI configuration space at offset 90h and is defined below. The usage model for this
register is described in subsequent sections.
4.1.1.1 MAP – Address Map Register – Offset 90h
This register is set by BIOS during POST. The exact value programmed into this register is based
on a BIOS setup option. Dynamic modifications of this register by BIOS as a result of POST or
some other event (e.g., docking event) is not permitted, as the underlying operating system
software may not comprehend the new device topology and may result in undefined behavior.
Bit Type
7:3 RO
2:0 RW
Caution: Programming the MAP.MV register with values other than those specified above will result in
undefined hardware behavior.
Note: The P-ATA host controller does not implement this register.
14
Reset
0 Reserved
Map Value (MV): The value in the bits below indicate the address range the
SATA
port responds to, and whether or not the P-ATA and
.
combined
Bits
Non-combined, SATA Port 0 is primary master, SATA Port 1 is
000
secondary master
Non-combined, SATA Port 0 is secondary master, SATA Port 1
000
001
is primary master
Combined, SATA Port 0 is primary master, SATA Port 1 is
100
primary slave, P-ATA is secondary
Combined, SATA Port 0 is primary slave, SATA Port 1 is
101
primary master, P-ATA is secondary
Combined, P-ATA is primary, SATA Port 0 is secondary master,
110
SATA Port 1 is secondary slave
Combined, P-ATA is primary, SATA Port 0 is secondary slave,
111
SATA Port 1 is secondary master
Description
SATA
Mapping
SATA Programmer's Reference Manual
R
functions are