Ps Power-On And System Reset Pushbuttons - Xilinx ZC702 User Manual

PS Power-On and System Reset Pushbuttons

[Figure 1-2, callout 27]
Figure 1-28 shows the reset circuitry for the processing system.
X-Ref Target - Figure 1-28
R179 R180 R181
10.0 K 10.0 K 10.0 K
0.1Ω 0.1Ω 0.1Ω
1% 1% 1%
SW1
2
PS_POR_B
1
SW2 2
PS_SRST_B 1
Depressing and then releasing pushbutton SW1 causes PS_POR_B_SW to strobe Low.
This reset is used to hold the PS in reset until all PS power supplies are at the
PS_POR_B:
required voltage levels. It must be held Low through PS power-up. PS_POR_B should be
generated by the power supply
Depressing and then releasing pushbutton SW2 causes PS_SRST_B_SW to strobe Low.
This reset is used to force a system reset. It can be tied or pulled High, and can be
PS_SRST_B:
High during the PS supply power ramps.
Refer to the Zynq-7000 SoC Technical Reference Manual
concerning the resets.
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
VCC3V3 VCCMIO
R138 R139
8.06 K 8.06 K
0.1Ω 0.1Ω
1% 1%
2
3
6
7
13
4
J6
9
8
R178 R182
10.0 K 10.0 K
0.1Ω 0.1Ω
1% 1%
GND
Figure 1-28: PS Power On and System Reset Circuitry
power-good
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VCC3V3
U2
MAX16025
Dual Voltage Monitor
R92
and Sequencer
249
1
0.1Ω
VCC
1%
12
RST_B
IN1
PS_POR_B_SW
11
OUT1
IN2
10 PS_SRST_B_SW
OUT2
EN1
16
CDLY1
EN2
15
CDLY2
MR_B
14
CRESET
TOL
17
EPAD
TH0
5
GND
TH1
0.1 µf
25V
X5R
GND
signal.
(UG585)
Feature Descriptions
VCCMIO VCCMIO
R184
10.0 K
DS1
0.1Ω
1%
R183
10.0 K
0.1Ω
1% PS_POR_B
PS_SRST_B
J28
2
1 3
2
1
3
J27
GND
C3
0.1 µf
25V
X5R
C5
0.1 µf
25V
X5R
C4
UG850_c1_28_032719
[Ref 2] for information
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