Fpga Mezzanine (Fmc) Card Interface; Lpc Connectors J3 And J4 - Xilinx ZC702 User Manual

FPGA Mezzanine (FMC) Card Interface

[Figure 1-2, callout 24]
The ZC702 board supports the VITA 57.1 FPGA Mezzanine Card (FMC) specification
by providing subset implementations of low pin count (LPC) connectors at J3 and J4. Both
connectors use a 10 x 40 form factor that is partially populated with 160 pins. The
connectors are keyed so that a the mezzanine card faces away from the ZC702 board when
connected.
Connector Type:
• Samtec SEAF series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector.
For more information about SEAF series connectors, go to the Samtec website

LPC Connectors J3 and J4

[Figure 1-2, callout 24]
The 160-pin FMC LPC connector is shown in
The LPC connections between FMC1 (J3) and XC7Z020 SoC U1
FMC2 (J4) and XC7Z020 SoC U1
(GTX is not supported):
• 68 single-ended or 34 differential user-defined signals (34 LA pairs, LA00–LA33)
• 0 GTX transceivers
• 0 GTX clocks
• 2 differential clocks
• 61 ground and 9 power connections
FMC1 (J3) and FMC2 (J4) GA0 = GA1 = 0 (GND).
Note:
Table 1-28 shows the LPC connections between J3 and XC7Z020 SoC U1.
Table 1-28: LPC Connections, FMC1 (J3) to XC7Z020 SoC U1
FMC1
Net Name
J3 Pin
C2 NC
C3 NC
C6 NC
C7 NC
C10 FMC1_LPC_LA06_P
C11 FMC1_LPC_LA06_N
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
(Table 1-29) both implement a subset of this connectivity
I/O XC7Z020 FMC1
Standard (U1) Pin J3 Pin
D1
D4
D5
D8
LVCMOS25 J18 D9
LVCMOS25 K18 D11
www.xilinx.com
Figure B-1.
(Table
Net Name
PWRCTL2_VCC4A_PG
NC
NC
FMC1_LPC_LA01_CC_P
FMC1_LPC_LA01_CC_N
FMC1_LPC_LA05_P
Feature Descriptions
[Ref 6]
[Ref 28].
1-28) and between
I/O XC7Z020
Standard (U1) Pin
LVCMOS25 N19
LVCMOS25 N20
LVCMOS25 N17
54
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