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block-mode transfer
BTO unit
bus master
C
C
CLK10
CMOS
Commander
configuration registers
© National Instruments Corporation
An uninterrupted transfer of data elements in which the master sources only
the first address at the beginning of the cycle. The slave is then responsible
for incrementing the address on subsequent transfers so that the next
element is transferred to or from the proper storage location. In VME, the
data transfer may have no more than 256 elements; MXI does not have this
restriction.
Bus Timeout Unit; a functional module that times the duration of each data
transfer and terminates the cycle if the duration is excessive. Without the
termination capability of this module, a bus master attempt to access a
nonexistent slave could result in an indefinitely long wait for a slave
response.
A device that is capable of requesting the Data Transfer Bus (DTB) for the
purpose of accessing a slave device.
Celsius.
A 10 MHz, ± 100 ppm, individually buffered (to each module slot),
differential ECL system clock that is sourced from Slot 0 of a VXIbus
mainframe and distributed to Slots 1 through 12 on P2. It is distributed to
each slot as a single-source, single-destination signal with a matched delay
of under 8 ns.
Complementary Metal Oxide Semiconductor; a process used in making
chips.
A message-based device which is also a bus master and can control one or
more Servants.
A set of registers through which the system can identify a module device
type, model, manufacturer, address space, and memory requirements. In
order to support automatic system and memory configuration, the VXIbus
specification requires that all VXIbus devices have a set of such registers.
G-3
Glossary
PCI-MXI-2 for Linux
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