Watchdog For System Mcu - Tripp Lite SU60KX Manual

2 Theory of Operation (continued)
2.9 Bypass SCR Driver (continued)
(a) The bypass SCR driver signal "BYPSTS1" is controlled by MCU or "TOBYP_J" according to the signal "CENTRAL_OK."
(b) "CENTRAL_OK" is the output of MCU watchdog. If MCU is operating normally, "CENTRAL_OK" will be high and the bypass SCR driver
signal will be controlled by "BYPSTS" (1) (high active). If MCU is not operating normally, "CENTRAL_OK" will be low and the bypass SCR
driver signal will be controlled by "TOBYP_J" (high active).
(c) UM9 is a 45 kHz self-oscillator that can provide pulse signal for driver bypass SCR.
(d) The "TOBYP_J" signal is limited by "#TOBYP_I."

2.10 Watchdog for System MCU

Located at NH-SYS-M board (System MCU and Control Circuit)
SYS_RDY
(a) SYS_RDY (4) will send out a pulse to reset CM46. CM46 will then be recharged by 5V through RM88. "CENTRAL_OK" will maintain a high
level. If SYS_RDY (4) does not send out a pulse during a specifi c period (for example, during an MCU crash), then "CENTRAL_OK" will be
low.
(b) Test JUMP (CNM2): If CNM2 is shorted, then "CENTRAL_OK" will be low. If CNM2 is opened, "CENTRAL_OK" will stay high during
normal operation.
RM 71
CM 39
(4)
QM 3
RM 81
RM 86
1
2
DM 24
CNM 2
2.5X 2P
G1
5VS
LEDM1
LED(GRN)
5VS
CM 36
G1
4 3
R Q
2 7
TRIG DIS
5 6
CVolt THR
UM 3
TLC555C
CM 45
CM 46
G1
RM 89
RM 88
QM 5
58
CENTRAL_OK
(70)
5VS