C28 Reset Cause Register (Cresc) Register; C28 Reset Cause Register (Cresc) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

System Control Registers
Table 1-63. Master Reset Cause (MRESC) Register Field Descriptions (continued)
Bit Field
24 EXTGPIO
23-17 Reserved
16 MCLKNMI
15-6 Reserved
5 WDT1
4 SW
3 WDT0
2 Reserved
1 POR
0 XRS

1.13.3.4 C28 Reset Cause Register (CRESC) Register

15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-64. C28 Reset Cause Register (CRESC) Register Field Descriptions
Bit Field
15-5 Reserved
4 C28_NMIRSN
194
System Control and Interrupts
Value Description
External GPIO NMI Unserviced
0 NMIWD event caused a device reset since the previous POR.
Writing a "0" to this bit clears it.
1 External NMI input triggered a M3 NMI and this triggered the M3 NMIWD. M3 did not respond to
the NMI and the NMIWD fired a reset.
Reserved
Missing Clock Condition NMI Unserviced
0 No NMIWD event that caused a device reset since the previous POR.
Writing a "0" to this bit clears it.
1 Missing clock detection triggered a M3 NMI and this triggered the M3 NMIWD. M3 did not respond
to the NMI and the NMIWD fired a reset.
Reserved
Watchdog Timer 1 Reset
0 No WDT1 time out reset causing device reset since the previous POR.
Writing a "0" to this bit clears it.
1 M3 WDT1 timed out and caused a device reset.
Software NVIC Reset
0 No NVIC software reset request that caused a device reset since the previous POR.
Writing a "0" to this bit clears it.
1 SW reset request from the NVIC SYSRESETREQ register caused a device reset.
Watchdog Timer 0 Reset
0 No WDT0 time out reset fired since the previous POR.
Writing a "0" to this bit clears it.
1 M3 WDT0 timed out and caused a device reset.
Reserved
POR Reset
0 No POR reset fired indicating a POR condition.
Writing a "0" to this bit clears it.
1 Power-on reset caused a device reset.
External Reset Input
0 No external reset input since the previous POR.
Writing a "0" to this bit clears it.
1 External reset input pin caused a device reset.
Figure 1-53. C28 Reset Cause Register (CRESC) Register
R-0
Value Description
1 Reserved
C28 NMI WDOG reset. If set, indicates that C28 NMI WDOG caused the reset.
If '0' then there was no C28 NMI WDOG reset since the previous POR
0 Clears this bit.
1 No effect
Copyright © 2012–2019, Texas Instruments Incorporated
5 4 3
C28_NMIRSN POR
R/W-0 R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
2 1 0
XRS Reserved
R/W-0 R-0
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