I2Cmcs Register - Read-Only Status Register; I2Cmcs Register Field Descriptions - Read-Only Status Register - Texas Instruments SimpleLink MSP432E4 Technical Reference Manual

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19.5.2 I2CMCS Register (Offset = 0x4) [reset = 0x20]
I2C Master Control/Status (I2CMCS)
This register accesses status bits when read and control bits when written. When read, the status register
indicates the state of the I
operation.
The START bit generates the START or repeated START condition. The STOP bit determines if the cycle
stops at the end of the data cycle or continues to the next transfer cycle, which could be a repeated
START. To generate a single transmit cycle, the I2CMSA register is written with the desired address, the
R/S bit is cleared, and this register is written with ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1
to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt
becomes active and the data may be read from the I2CMDR register. When the I
master receiver mode, the ACK bit is normally set, causing the I
acknowledge automatically after each byte. This bit must be cleared when the I
no further data to be transmitted from the slave transmitter.
NOTE: After the CPU starts a transaction, up to 60% of the I
BUSY bit is set. Therefore, a delay is required before reading this bit.
NOTE: When reading the I2CMCS register to check the BUSY bit, also read the ADRACK and
DATACK bits, because these are cleared on register read, and status may be lost if they are
not checked on every read of the register.
Alternatively, the NACKRIS bit of the I2CMRIS register can be used to monitor NACK status.
I2CMCS as a read-only status register is shown in
I2CMCS as a write-only control register is shown in
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31 30
ACTDMARX ACTDMATX
R-0x0 R-0x0
23 22
15 14
7 6
CLKTO BUSBSY
R-0x0 R-0x0
Table 19-6. I2CMCS Register Field Descriptions — Read-Only Status Register
Bit Field
31 ACTDMARX
30 ACTDMATX
29-8 RESERVED
SLAU723A – October 2017 – Revised October 2018
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2
C bus controller. When written, the control register configures the I
Table.
Figure 19-17. I2CMCS Register — Read-Only Status Register
29 28
21 20
RESERVED
13 12
RESERVED
5 4
IDLE ARBLST
R-0x1 R-0x0
Type Reset
R 0x0
R 0x0
R 0x0
Copyright © 2017–2018, Texas Instruments Incorporated
2
C bus controller to transmit an
2
C clock period is required before the
Figure 19-17 and described in
Figure 19-18 and described in
27 26
RESERVED
R-0x0
19 18
R-0x0
11 10
R-0x0
3 2
DATACK ADRACK
R-0x0 R-0x0
Description
DMA RX Active Status.
0x0 = DMA RX is not active
0x1 = DMA RX is active.
DMA TX Active Status.
0x0 = DMA TX is not active
0x1 = DMA TX is active.
Inter-Integrated Circuit (I
I2C Registers
2
C controller
2
C module operates in
2
C bus controller requires
Table 19-6.
Table 19-7.
25 24
17 16
9 8
1 0
ERROR BUSY
R-0x0 R-0x0
1337
2
C) Interface