Sdram Timing Register (Sdtimr); Sdram Timing Register (Sdtimr) Field Descriptions - Texas Instruments TMS320C642x DSP User Manual

DDR2 Memory Controller Registers
4.4

SDRAM Timing Register (SDTIMR)

The SDRAM timing register (SDTIMR) configures the DDR2 memory controller to meet many of the AC
timing specification of the DDR2 memory. The SDTIMR register is programmable only when the
TIMUNLOCK bit is set to 1 in the SDBCR. Note that DDR_CLK is equal to the period of the DDR_CLK
signal. See the DDR2 memory data sheet for information on the appropriate values to program each field.
The SDTIMR is shown in
31
T_RFC
R/W-1Ah
15
T_RAS
R/W-9h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field Value
31-25 T_RFC 0-7Fh
24-22 T_RP 0-7h
21-19 T_RCD 0-7h
18-16 T_WR 0-7h
15-11 T_RAS 0-1Fh
10-6 T_RC 0-1Fh
5-3 T_RRD 0-7h
2 Reserved 0
1-0 T_WTR 0-3h
46 DDR2 Memory Controller
Figure 22 and described in
Figure 22. SDRAM Timing Register (SDTIMR)
25
11 10
T_RC
R/W-Eh
Table 28. SDRAM Timing Register (SDTIMR) Field Descriptions
Description
Specifies the minimum number of DDR_CLK cycles from a refresh or load mode command to a refresh
or activate command, minus 1. Corresponds to the t
Calculate by:
T_RFC = (t /DDR_CLK period) - 1
rfc
Specifies the minimum number of DDR_CLK cycles from a precharge command to a refresh or activate
command, minus 1. Corresponds to the t
T_RP = (t /DDR_CLK period) - 1
rp
Specifies the minimum number of DDR_CLK cycles from an activate command to a read or write
command, minus 1. Corresponds to the t
T_RCD = (t /DDR_CLK period) - 1
rcd
Specifies the minimum number of DDR_CLK cycles from the last write transfer to a precharge
command, minus 1. Corresponds to the t
T_WR = (t /DDR_CLK period) - 1
wr
When the value of this field is changed from its previous value, the initialization sequence will begin.
Specifies the minimum number of DDR_CLK cycles from an activate command to a precharge
command, minus 1. Corresponds to the t
T_RAS = (t /DDR_CLK period) - 1
ras
T_RAS must be greater than or equal to T_RCD.
Specifies the minimum number of DDR_CLK cycles from an activate command to an activate
command, minus 1. Corresponds to the t
T_RC = (t /DDR_CLK period) - 1
rc
Specifies the minimum number of DDR_CLK cycles from an activate command to an activate command
in a different bank, minus 1. Corresponds to the t
Calculate by:
T_RRD = (t /DDR_CLK period) - 1
rrd
Note: for an 8 bank DDR2 device this field must be equal to ((4
Reserved
Specifies the minimum number of DDR_CLK cycles from the last write to a read command, minus 1.
Corresponds to the t AC timing parameter in the DDR2 data sheet. Calculate by:
wtr
T_WTR = (t /DDR_CLK period) - 1
wtr
Table 28.
24 22 21
T_RP
R/W-5h
6 5
AC timing parameter in the DDR2 data sheet.
rfc
AC timing parameter in the DDR2 data sheet. Calculate by:
rp
AC timing parameter in the DDR2 data sheet. Calculate by:
rcd
AC timing parameter in the DDR2 data sheet. Calculate by:
wr
AC timing parameter in the DDR2 data sheet. Calculate by:
ras
AC timing parameter in the DDR2 data sheet. Calculate by:
rc
AC timing parameter in the DDR2 data sheet.
rrd
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19 18
T_RCD T_WR
R/W-5h R/W-3h
3 2 1
T_RRD Rsvd T_WTR
R/W-3h R-0 R/W-3h
t ) + (2 t )) / (4 t ) - 1.
RRD CK CK
SPRUEM4A – November 2007
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