Siemens 7SR10 Argus Series Manual page 7

List of Figures
Figure 2-1 7SR10 Argus Overcurrent Relay with Control Push Buttons ............................................................... 15
Figure 2-2 7SR10 Non-Directional and Directional Overcurrent Relay with Connectors ....................................... 17
Figure 2-3 Relay Rating Label ........................................................................................................................... 18
Figure 2-4 Fascia Relay Rating Label ................................................................................................................ 18
Figure 2-5 Safety Symbols ................................................................................................................................ 18
Figure 2-6 Close up of Relay Identifier ............................................................................................................... 19
Figure 2-7 LED Indication Label ........................................................................................................................ 20
Figure 2-8 Binary Input Logic ............................................................................................................................. 21
Figure 2-9 Binary Output Logic .......................................................................................................................... 22
Figure 2-10 Start-up Counter Meter ..................................................................................................................... 23
Figure 2-11 Unexpected Restarts Lockout Text .................................................................................................... 23
Figure 2-12 Start-up Events ................................................................................................................................ 24
Figure 3-1 Logic Diagram: Directional Overcurrent Element (67)......................................................................... 26
Figure 3-2 Logic Diagram: Instantaneous Over-current Element ......................................................................... 27
Figure 3-3 Logic Diagram: Time Delayed Overcurrent Element ........................................................................... 28
Figure 3-4 Logic Diagram: Voltage Controlled Overcurrent Protection ................................................................. 29
Figure 3-5 Logic Diagram: Derived Directional Earth Fault Element .................................................................... 30
Figure 3-6 Logic Diagram: Derived Instantaneous Earth Fault Element ............................................................... 31
Figure 3-7 Logic Diagram: Derived Time Delayed Earth Fault Protection ............................................................ 33
Figure 3-8 Logic Diagram: Measured Directional Earth Fault Protection .............................................................. 34
Figure 3-9 Logic Diagram: Measured Instantaneous Earth-fault Element ............................................................ 35
Figure 3-10 Logic Diagram: Measured Time Delayed Earth Fault Element (51G) .................................................. 36
Figure 3-11 Logic Diagram: SEF Directional Element (67SEF) ............................................................................. 37
Figure 3-12 Logic Diagram: 7SR10 SEF Instantaneous Element .......................................................................... 38
Figure 3-13 Logic Diagram: 7SR10 SEF Instantaneous Element .......................................................................... 38
Figure 3-14 Logic Diagram: 7SR10 SEF Time Delayed Element (51SEF) ............................................................. 39
Figure 3-15 Logic Diagram: 7SR10 SEF Time Delayed Element (51SEF) ............................................................. 39
Figure 3-16 Logic Diagram: High Impedance REF (64H) ...................................................................................... 40
Figure 3-17 Logic Diagram: Cold Load Settings (51c)........................................................................................... 41
Figure 3-18 Logic Diagram: Negative Phase Sequence Overcurrent (46NPS) ....................................................... 42
Figure 3-19 Logic Diagram: Phase Current Inputs Undercurrent Detector (37) ...................................................... 42
Figure 3-20 Logic Diagram: Earth Current Inputs Undercurrent Detector (37G) ..................................................... 43
Figure 3-21 Logic Diagram: Sensitive Earth Current Inputs Undercurrent Detector (37SEF) .................................. 43
Figure 3-22 Logic Diagram: Thermal Overload Protection (49) ............................................................................. 44
Figure 3-23 Logic Diagram: Under/Over Voltage Elements (27/59) ....................................................................... 45
Figure 3-24 Logic Diagram: NPS Overvoltage Protection (47) .............................................................................. 45
Figure 3-25 Logic Diagram: Neutral Overvoltage Element (59N) ........................................................................... 46
Figure 3-26 Logic Diagram: Under/Over Frequency Detector (81)......................................................................... 47
Figure 3-27 Logic Diagram: Power Protection (32) ............................................................................................... 48
Figure 3-28 Logic Diagram: Sensitive Power Protection (32S) .............................................................................. 49
Figure 3-29 Logic Diagram: Power Factor Protection (55) .................................................................................... 50
Figure 4-1 Typical AR Sequence with 3 Inst and 1 Delayed trip .......................................................................... 53
Figure 4-2 Basic Auto-Reclose Sequence Diagram ............................................................................................ 57
Figure 4-3 Sequence Diagram: Quick Logic PU/DO Timers (Counter Reset Mode Off) ........................................ 58
Figure 4-4 Logic Diagram: Circuit Breaker Status ............................................................................................... 61
Figure 5-1 Logic Diagram: Circuit Breaker Fail Protection (50BF) ....................................................................... 62
Figure 5-2 Logic Diagram: Harmonic Block Feature (81HBL2) ............................................................................ 63
Figure 5-3 Logic Diagram: Total Harmonic Distortion Supervision Element (81THD) ........................................... 64
Figure 5-4 Logic Diagram: VT Supervision Function (60VTS) ............................................................................. 65
Figure 5-5 Logic Diagram: CT Supervision Function (60CTS) ............................................................................. 66
©2018 Siemens Protection Devices Limited
7SR10 Description of Operation
Chapter 1 Page 4 of 77