Figure 3-3 Logic Diagram: Time Delayed Overcurrent Element - Siemens 7SR10 Argus Series Manual

Operation of the time delayed overcurrent elements can be inhibited from:
Inhibit 51-n
79 P/F Inst Trips: 51-n
51c
51-n Inrush Action: Block
51-n VTSAction: Inhibit
AUTORECLOSE
79 P/F Inst Trips
= 51-n
79 P/F Prot'n Trip n
= Delayed
51-n Inrush
Action
Off
Inhibit
51-n Dir Control
Non-Dir
Forward
Reverse
IL1 Fwd
IL1 Rev
IL2 Fwd
IL2 Rev
IL3 Fwd
IL3 Rev
Figure 3-3
©2018 Siemens Protection Devices Limited
A binary or virtual input.
When 'delayed' trips only are allowed in the auto-reclose sequence
(79 P/F Prot'n Trip n = Delayed).
Activation of the cold load settings.
Operation of the inrush current detector function.
Operation of the VT Supervision function.
See Voltage Controlled
Overcurrent (51V)
51-n Element
Enabled
Disabled
&
&
Inhibit 51-n
51c
&
&
L1 81HBL2
L1 Dir En
&
&
L2 81HBL2
L2 Dir En
&
&
L3 81HBL2
L3 Dir En
50/51
Measurement
IL1
IL2
IL3
&
&
&
&
&
&
Logic Diagram: Time Delayed Overcurrent Element
L1
L2
L3
51-n Setting
51-n Charact
51-n Time Mult
51-n Delay (DTL)
51-n Min. Operate Time
51-n Follower DTL
51-n Reset
c
c
Pickup
trip
c
Pickup
trip
c
Pickup
trip
51-n VTS Action
Off
Non Dir
Inhibit
&
VT Fail
≥1
≥1
≥1
7SR10 Description of Operation
≥1
General Pickup
≥1
51-n
If directional elements are not
present this block is omitted and all
'Lx Dir En' signals are set TRUE.
&
&
≥1
L1 Dir En
&
≥1
L2 Dir En
&
≥1
L3 Dir En
Chapter 1 Page 28 of 77