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AC timing specifications referenced to SDCLK assume
SDRAM control register bit 3 is 0. After reset this bit is set.
23.3.1 Clock Input and Output Timing Specifications
Table 23-6 lists clock input and output timings.
Table 23-6. Clock Input and Output Timing Specifications
Name
Frequency of operation
C1
CLKIN period (T)
2
C2
CLKIN fall time (from V
2
C3
CLKIN rise time (from V
C4
CLKIN duty cycle (measured at 1.5 V)
3
C4a
CLKIN pulse width high (measured at 1.5 V)
3
C4b
CLKIN pulse width low (measured at 1.5 V)
1
The clock period is referred to as T in the electrical specifications. The time for T is always in nS. Timing
specifications can be given in terms of T. For example, 2T+5 nS
2
Specification values are not tested.
3
Specification values listed are for maximum frequency of operation.
Clock input and output timings listed in Table 23-6 are shown in Figure 23-1.
CLKIN
(input)
23.3.2 Processor Bus Input Timing Specifications
Table 23-7 lists processor bus input timings.
All processor bus timings are synchronous; that is, input
setup/hold and output delay with respect to the rising edge of a
reference clock. The reference clock is the SDCLK output.
All other timing relationships can be derived from these values.
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Characteristic
1
= 2.4 V to V
= 0.5 V)
h
l
= 0.5 V to V
= 2.4 V)
l
h
C1
C4a
Figure 23-1. Clock Input Timing Diagram
NOTE:
Chapter 23. Electrical Characteristics
AC Electrical Specifications
0–66 MHz
Min
Max
0
66.00
15
—
—
2
—
2
45
55
6.75
8.25
6.75
8.25
C2
C3
V
h
V
l
C4b
Unit
MHz
nS
nS
nS
%
nS
nS
23-5
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