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Bits
Name
7–6
CM
Channel mode. Selects a channel mode. Section 16.5.3, "Looping Modes," describes individual
modes.
00 Normal
01 Automatic echo
10 Local loop-back
11 Remote loop-back
5
TxRTS Transmitter ready-to-send. Controls negation of RTS to automatically terminate a message
transmission when the transmitter is disabled after completion of a transmission. Attempting to
program a receiver and transmitter in the same channel for RTS control is not permitted and disables
RTS control for both.
0 The transmitter has no effect on RTS.
1 When the transmitter is disabled after transmission completes, setting this bit automatically clears
UOP[RTS] one bit time after any characters in the channel transmitter shift and holding registers are
completely sent, including the programmed number of stop bits.
4
TxCTS Transmitter clear-to-send. If both TxCTS and TxRTS are enabled, TxCTS controls the operation of the
transmitter.
0 CTS has no effect on the transmitter.
1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to
send a character. If CTS is asserted, the character is sent; if it is negated, the channel TxD remains
in the high state and transmission is delayed until CTS is asserted. Changes in CTS as a character is
being sent do not affect its transmission.
3–0
SB
Stop-bit length control. Selects the length of the stop bit appended to the transmitted character.
Stop-bit lengths of 9/16th to 2 bits are programmable for 6–8 bit characters. Lengths of 1 1/16th to 2
bits are programmable for 5-bit characters. In all cases, the receiver checks only for a high condition at
the center of the first stop-bit position, that is, one bit time after the last data bit or after the parity bit, if
parity is enabled. If an external 1x clock is used for the transmitter, clearing bit 3 selects one stop bit
and setting bit 3 selects 2 stop bits for transmission.
SB
0000 1.063
0001 1.125
0010 1.188
0011 1.250
16.3.3 UART Status Registers (USRn)
The USRn, Figure 16-4, shows status of the transmitter, the receiver, and the FIFO.
7
Field
RB
Reset
R/W
Address
Table 16-3. UMR2n Field Descriptions
5 Bits
6–8 Bits
SB
0.563
0100
0.625
0101
0.688
0110
0.750
0111
6
5
FE
PE
MBAR + 0x104 (USR0), 0x144 (USR1)
Figure 16-4. UART Status Registers (USRn)
Chapter 16. UART Modules
Description
5 Bits
6–8 Bits
SB
1.313
0.813
1000
1.375
0.875
1001
1.438
0.938
1010
1.500
1.000
1011
4
3
OE
TxEMP
TxRDY
0000_0000
Read only
Register Descriptions
5–8 Bits
SB
5–8 Bits
1.563
1100
1.813
1.625
1101
1.875
1.688
1110
1.938
1.750
1111
2.000
2
1
FFULL
RxRDY
0
16-7
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