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S0
SDCLK
CSn
A[22:0]
OE
(H)
R/W
BS[3:0]
D[31:0]
TA
(H)
TEA
Figure 23-5. SRAM Bus Cycle Terminated by TEA
Figure 23-6 shows reset and mode Select/HIZ configuration timing showing parameters
listed in Table 23-8.
SDCLK
RSTI
Mode selects
(BUSW[1,0],
WSEL,HIZ)
Figure 23-6. Reset and Mode Select/HIZ Configuration Timing
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
S1
S2
S3
B6a
B8
B6c
B6b
B1c
B3
B1f
Chapter 23. Electrical Characteristics
AC Electrical Specifications
SW0
S4
S5
B7a
B9
B7a
Reset is asynchronous.
Assert for at least 2
consecutive SDCLK
rising edges
B2e
SW1
S0
S1
B7b
B2d
23-11
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