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CPU Clock and Reset Signals
19.5.6 Bypass
Bypass is a Motorola test mode signal. This signal should be left unconnected.
19.5.7 SDRAM Row Address Strobe (RAS0)
RAS0 is the SDRAM row address strobe output.
19.5.8 SDRAM Column Address Strobe (CAS0)
CAS0 is the SDRAM column address strobe output.
19.5.9 SDRAM Clock (SDCLK)
The SDRAM clock output (SDCLK) is the same frequency as the CPU clock.
19.5.10 SDRAM Write Enable (SDWE)
This output is the SDRAM write enable.
19.5.11 SDRAM Clock Enable (SDCLKE)
This output is the SDRAM clock enable.
19.5.12 SDRAM Bank Selects (SDBA[1:0])
These outputs are the SDRAM bank select signals.
19.5.13 SDRAM Row Address 10 (A10)/A10 Precharge
(A10_PRECHG)
This output is the SDRAM row address 10 and the precharge strobe.
19.6 CPU Clock and Reset Signals
This section describes clock and reset signals in the CPU.
19.6.1 RSTI
RSTI is the primary reset input to the device. Asserting RSTI immediately resets the CPU
and peripherals. However, the reset of the SDRAM controller and hence SDRAM contents
depend on DRESETEN. Asserting RSTI also causes RSTO to be asserted for 32K CPU
clock cycles.
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MCF5272 User's Manual
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